公开(公告)号：US20240250061A1

公开(公告)日：2024-07-25

申请号：US18624954

申请日：2024-04-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chi Lin ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L23/00 ,  B23K26/362 ,  H01L21/3213 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/80 ,  B23K26/362 ,  H01L21/32136 ,  H01L24/03 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/37001

Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

公开(公告)号：US11854990B2

公开(公告)日：2023-12-26

申请号：US17176299

申请日：2021-02-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/81 ,  H01L24/97 ,  H01L24/16 ,  H01L25/0652 ,  H01L2221/68345 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/07 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2224/73203 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

公开(公告)号：US20230343747A1

公开(公告)日：2023-10-26

申请号：US18338013

申请日：2023-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Tsu Chung ,  Ku-Feng Yang ,  Yung-Chi Lin ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683 ,  H01L21/82

CPC classification number: H01L25/0652 ,  H01L23/481 ,  H01L24/80 ,  H01L25/50 ,  H01L21/6836 ,  H01L21/82 ,  H01L24/08 ,  H01L2221/68327 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor package including an improved isolation bonding film and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first die bonded to a package substrate, the first die including vias extending through a substrate, the vias extending above a top surface of the substrate; a first dielectric film extending along a top surface of the package substrate, along the top surface of the substrate, and along sidewalls of the first die, the vias extending through the first dielectric film; a second die bonded to the first dielectric film and the vias; and an encapsulant over the package substrate, the first die, the first dielectric film, and the second die.

公开(公告)号：US11063008B2

公开(公告)日：2021-07-13

申请号：US16571212

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chi Lin ,  Chen-Hua Yu ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/367 ,  H01L23/535 ,  H01L23/58 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, an interconnection structure, a through substrate via, an insulating layer, a conductive pillar, a dummy conductive pillar, a passivation layer and a bonding pad. The interconnection structure is disposed over the semiconductor substrate. The through substrate via at least partially extends in the semiconductor substrate along a thickness direction of the semiconductor substrate, and electrically connects to the interconnection structure. The insulating layer is disposed over the interconnection structure. The conductive pillar is disposed in the insulating layer, and electrically connected to the through substrate via. The dummy conductive pillar is disposed in the insulating layer, and laterally separated from the conductive pillar. The passivation layer is disposed over the insulating layer. The bonding pad is disposed in the passivation layer, and electrically connected to the conductive pillar.

公开(公告)号：US20210167018A1

公开(公告)日：2021-06-03

申请号：US17176299

申请日：2021-02-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/14 ,  H01L25/065

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

公开(公告)号：US20210050316A1

公开(公告)日：2021-02-18

申请号：US17073533

申请日：2020-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao Yun Lo ,  Lin-Chih Huang ,  Tasi-Jung Wu ,  Hsin-Yu Chen ,  Yung-Chi Lin ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/00 ,  H01L23/48

Abstract: A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.

公开(公告)号：US20240387393A1

公开(公告)日：2024-11-21

申请号：US18786966

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

公开(公告)号：US20210327866A1

公开(公告)日：2021-10-21

申请号：US16934870

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Yung-Chi Lin ,  Wen-Chih Chiou

IPC: H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

公开(公告)号：US20170317033A1

公开(公告)日：2017-11-02

申请号：US15141836

申请日：2016-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hui Wang ,  Chih-Hung Cheng ,  Yung-Chi Lin ,  Wen-Chih Chiou

IPC: H01L23/544 ,  H01L21/3105 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L21/3105 ,  H01L21/6835 ,  H01L24/11 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2224/11002 ,  H01L2224/11005

Abstract: A package carrier includes a carrier and a light absorption layer. The light absorption layer is disposed on the carrier. The light absorption layer includes a notch at the periphery of the carrier, and the notch is light transmissive so as to expose the carrier to light in a normal direction of the carrier. A semiconductor manufacturing process is also provided.

公开(公告)号：US20250062204A1

公开(公告)日：2025-02-20

申请号：US18404266

申请日：2024-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yan-Zuo Tsai ,  Ming-Tsu Chung ,  Yang-Chih Hsueh ,  Yung-Chi Lin

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L23/16 ,  H01L23/528

Abstract: A package includes a first die over and bonded to a first side of a second die, where the second die includes a first substrate, a first interconnect structure over the first substrate, a seal ring disposed within the first interconnect structure, first dummy through substrate vias (TSVs) extending through edge regions of the first substrate of the second die and in physical contact with the seal ring, and functional TSVs extending through a central region of the first substrate of the second die.