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公开(公告)号：US11312615B2
公开(公告)日：2022-04-26
申请号：US16942055
申请日：2020-07-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ting-Jung Chen
Abstract: Various embodiments of the present disclosure are directed towards a method to roughen a crystalline layer. A crystalline layer is deposited over a substrate. A mask material is diffused into the crystalline layer along grain boundaries of the crystalline layer. The crystalline layer and the mask material may, for example, respectively be or comprise polysilicon and silicon oxide. Other suitable materials are, however, amenable. An etch is performed into the crystalline layer with an etchant having a high selectivity for the crystalline layer relative to the mask material. The mask material defines micro masks embedded in the crystalline layer along the grain boundaries. The micro masks protect underlying portions of the crystalline layer during the etch, such that the etch forms trenches in the crystalline layer where unmasked by the micro masks.
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公开(公告)号：US12272585B2
公开(公告)日：2025-04-08
申请号：US17241666
申请日：2021-04-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ting-Jung Chen , Shih-Wei Lin , Lee-Chuan Tseng
IPC: H01L21/683 , C23C14/50 , C23C14/54 , C23C14/58 , C23C16/458 , C23C16/46 , H01J37/32 , H01L21/67 , H01L21/768
Abstract: In some embodiments, the present disclosure relates to a process tool that includes a chamber housing defined by a processing chamber, and a wafer chuck structure arranged within the processing chamber. The wafer chuck structure is configured to hold a wafer during a fabrication process. The wafer chuck includes a lower portion and an upper portion arranged over the lower portion. The lower portion includes trenches extending from a topmost surface towards a bottommost surface of the lower portion. The upper portion includes openings that are holes, extend completely through the upper portion, and directly overlie the trenches of the lower portion. Multiple of the openings directly overlie each trench. Further, cooling gas piping is coupled to the trenches of the lower portion of the wafer chuck structure, and a cooling gas source is coupled to the cooling gas piping.
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公开(公告)号：US20230357000A1
公开(公告)日：2023-11-09
申请号：US17811109
申请日：2022-07-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ting-Jung Chen
CPC classification number: B81C1/00158 , B81B3/0021 , B81B2201/0257 , B81B2203/0127 , B81B2203/0315 , B81B2203/0353 , B81B2203/04 , B81C2201/0125 , B81C2201/0132 , B81C2201/0133 , B81C2201/014 , B81C2201/0176
Abstract: A membrane is formed through processes including depositing a first piezoelectrical layer, depositing a first electrode layer over the first piezoelectrical layer, patterning the first electrode layer to form a first electrode, depositing a second piezoelectrical layer over the first electrode, depositing a second electrode layer over the second piezoelectrical layer, patterning the second electrode layer to form a second electrode, and depositing a third piezoelectrical layer over the second electrode. The third piezoelectrical layer, the second piezoelectrical layer, and the first piezoelectrical layer are etched to form a through-hole. The through-hole is laterally spaced apart from the first electrode and the second electrode. A first contact plug and a second contact plug are then formed to electrically connect to the first electrode and the second electrode, respectively.
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公开(公告)号：US11661337B2
公开(公告)日：2023-05-30
申请号：US17176353
申请日：2021-02-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ting-Jung Chen , Lee-Chuan Tseng
CPC classification number: B81C1/00166 , B81C1/00031 , H01L21/4857
Abstract: An integrated circuit (IC) device includes: a first substrate; a dielectric layer disposed over the first substrate; and a second substrate disposed over the dielectric layer. The second substrate includes anchor regions comprising silicon extending upwards from the dielectric layer, and a series of interdigitated fingers extend from inner sidewalls of the anchor regions. The interdigitated fingers extend generally in parallel with one another in a first direction and have respective finger lengths that extend generally in the first direction. A plurality of peaks comprising silicon is disposed on the dielectric layer directly below the respective interdigitated fingers. The series of interdigitated fingers are cantilevered over the plurality of peaks. A first peak is disposed below a base of a finger and has a first height, and a second peak is disposed below a tip of the finger and has a second height less than the first height.
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公开(公告)号：US11557710B2
公开(公告)日：2023-01-17
申请号：US16250049
申请日：2019-01-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ting-Jung Chen , Ming Chyi Liu
IPC: H01L41/047 , H01L41/18 , H01L41/083 , H01L41/293 , H01L41/332
Abstract: Various embodiments of the present disclosure are directed towards a method for forming a piezoelectric device including a piezoelectric membrane and a plurality of conductive layers. The method includes forming the plurality of conductive layers in the piezoelectric membrane, the plurality of conductive layers are vertically offset one another. A masking layer is formed over the piezoelectric membrane. An etch process is performed according to the masking layer to concurrently expose an upper surface of each conductive layer in the plurality of conductive layers. A plurality of conductive vias are formed over the upper surface of the plurality of conductive layers.
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Patent Agency Ranking
公开(公告)号：US11482663B2
公开(公告)日：2022-10-25
申请号：US16879565
申请日：2020-05-20
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Ting-Jung Chen
IPC: H01L41/293 , H01L41/047 , H01L41/083 , H01L41/35
Abstract: A method for forming a MEMS device is provided. The method includes forming a stack of piezoelectric films and metal films on a base layer, wherein the piezoelectric films and the metal films are arranged in an alternating manner. The method also includes forming a first trench in the stack of the piezoelectric films and the metal films. The method further includes forming at least one void at the side wall of the first trench. In addition, the method includes forming a spacer structure in the at least one void. The method further includes forming a contact in the first trench after the formation of the spacer structure.
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公开(公告)号：US10766763B2
公开(公告)日：2020-09-08
申请号：US16392844
申请日：2019-04-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Wei Lin , Chang-Ming Wu , Ting-Jung Chen
Abstract: The present disclosure relates to a microphone. In some embodiments, the microphone may comprise a substrate, a diaphragm, a backplate, and a sidewall stopper. The substrate has an opening disposed through the substrate. The diaphragm is disposed over the substrate and facing the opening of the substrate. The diaphragm has a venting hole overlying the opening of the substrate. A backplate is disposed over and spaced apart from the diaphragm. A sidewall stopper is disposed along a sidewall of the venting hole of the diaphragm and thus is not limited by a distance between the movable part and the stable part. Also, the sidewall stopper does not alternate the shape of movable part, and thus will less likely introduce crack to the movable part. In some embodiments, the sidewall stopper may be formed like a sidewall stopper by a self-alignment process, such that no extra mask is needed.
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公开(公告)号：US20200102209A1
公开(公告)日：2020-04-02
申请号：US16392844
申请日：2019-04-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Wei Lin , Chang-Ming Wu , Ting-Jung Chen
Abstract: The present disclosure relates to a microphone. In some embodiments, the microphone may comprise a substrate, a diaphragm, a backplate, and a sidewall stopper. The substrate has an opening disposed through the substrate. The diaphragm is disposed over the substrate and facing the opening of the substrate. The diaphragm has a venting hole overlying the opening of the substrate. A backplate is disposed over and spaced apart from the diaphragm. A sidewall stopper is disposed along a sidewall of the venting hole of the diaphragm and thus is not limited by a distance between the movable part and the stable part. Also, the sidewall stopper does not alternate the shape of movable part, and thus will less likely introduce crack to the movable part. In some embodiments, the sidewall stopper may be formed like a sidewall stopper by a self-alignment process, such that no extra mask is needed.
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公开(公告)号：US12043537B2
公开(公告)日：2024-07-23
申请号：US16990106
申请日：2020-08-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Wei Lin , Chang-Ming Wu , Ting-Jung Chen
CPC classification number: B81B3/001 , B81B1/004 , B81B3/0021 , B81C1/00158 , B81C1/00531 , B81C1/00571 , B81B2201/0257 , B81B2203/0127 , B81B2203/053
Abstract: The present disclosure provides a method of manufacturing a MEMS device. In some embodiments, a first interlayer dielectric layer is formed over a substrate, and a diaphragm is formed over the first interlayer dielectric layer. Then, a second interlayer dielectric layer is formed over the diaphragm. A first etch is performed to form an opening through the second interlayer dielectric layer and the diaphragm and reaching into an upper portion of the first interlayer dielectric layer. A second etch is performed to the first interlayer dielectric layer and the second interlayer dielectric layer to form recesses above and below the diaphragm and to respectively expose a portion of a top surface and a portion of a bottom surface of the diaphragm. A sidewall stopper is formed along a sidewall of the diaphragm into the recesses of the first interlayer dielectric layer and the second interlayer dielectric layer.
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公开(公告)号：US20220033246A1
公开(公告)日：2022-02-03
申请号：US16942055
申请日：2020-07-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ting-Jung Chen
Abstract: Various embodiments of the present disclosure are directed towards a method to roughen a crystalline layer. A crystalline layer is deposited over a substrate. A mask material is diffused into the crystalline layer along grain boundaries of the crystalline layer. The crystalline layer and the mask material may, for example, respectively be or comprise polysilicon and silicon oxide. Other suitable materials are, however, amenable. An etch is performed into the crystalline layer with an etchant having a high selectivity for the crystalline layer relative to the mask material. The mask material defines micro masks embedded in the crystalline layer along the grain boundaries. The micro masks protect underlying portions of the crystalline layer during the etch, such that the etch forms trenches in the crystalline layer where unmasked by the micro masks.
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