公开(公告)号：US11894381B2

公开(公告)日：2024-02-06

申请号：US16665791

申请日：2019-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung Chen ,  Tsung-Lin Lee ,  Chung-Ming Lin ,  Wen-Chih Chiang ,  Cheng-Hung Wang

IPC: H01L27/12 ,  H01L21/74 ,  H01L23/535

CPC classification number: H01L27/1203 ,  H01L21/743 ,  H01L23/535

Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.

公开(公告)号：US12074169B2

公开(公告)日：2024-08-27

申请号：US17876409

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung Chen ,  Tsung-Lin Lee ,  Chung-Ming Lin ,  Wen-Chih Chiang ,  Cheng-Hung Wang

IPC: H01L21/74 ,  H01L23/535 ,  H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/743 ,  H01L23/535

Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.