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公开(公告)号：US20170317625A1
公开(公告)日：2017-11-02
申请号：US15142219
申请日：2016-04-29
摘要： A voltage regulator includes an output transistor, an error amplifier coupled to the output transistor, a cascode transistor coupled to the output transistor in series, and a cascode bias circuit coupled to the cascode transistor and the output transistor. The output transistor is configured to generate an output signal at a first voltage. The error amplifier is configured to receive a reference signal. The cascode bias circuit is configured to bias the cascode transistor such that, in response to a drain-to-source short circuit of the output transistor, the cascode transistor generates the output signal at the first voltage.
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公开(公告)号：US20190341917A1
公开(公告)日：2019-11-07
申请号：US15969034
申请日：2018-05-02
发明人： Xiong LI , Toru TANAKA
摘要： A system comprises a gate driver that is configured to couple to a transistor disposed in a transistor module via a first pin. The gate driver comprises a duty cycle measurement circuit having a first input terminal and a first output terminal, the first input terminal coupled to a second pin via an isolator. The duty cycle measurement circuit comprises a flip-flop, a counter, a shift register, and a comparator. The system comprises an analog to digital converter circuit having a second input terminal, a second output terminal, and a reference terminal, the second input terminal coupled to a third pin configured to couple to a temperature-sensitive device disposed in the transistor module, the second output terminal coupled to a fourth pin via the isolator, and the reference terminal coupled to the first output terminal.
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公开(公告)号：US20190296695A1
公开(公告)日：2019-09-26
申请号：US15934467
申请日：2018-03-23
摘要： An offset drift compensation circuit for correcting offset drift that changes with temperature. In one example, offset drift compensation circuit includes a low temperature offset compensation circuit and a high temperature offset circuit. The low temperature offset compensation circuit is configured to compensate for drift in offset at a first rate below a selected temperature. The high temperature offset compensation circuit is configured to compensate for drift in offset at a second rate above the selected temperature. The first rate is different from the second rate.
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公开(公告)号：US20170317619A1
公开(公告)日：2017-11-02
申请号：US15142852
申请日：2016-04-29
IPC分类号： H02P6/12 , H03K17/687
摘要： A gate driver circuit includes a comparator and a gate driver. The comparator is configured to detect a short circuit in a first power field effect transistor (FET). The gate driver is configured to drive a gate of the first power FET by generating a first signal at a first drive current. In response to the comparator detecting a short circuit in the first power FET, the gate driver is further configured to pulse the first signal at a first pulldown current. After the pulse has ended, the gate driver is further configured to drive the gate of the first power FET at a first hold current. The first hold current is less than the first pulldown current.
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公开(公告)号：US20180343009A1
公开(公告)日：2018-11-29
申请号：US15854515
申请日：2017-12-26
发明人： Xiong LI , Toru TANAKA
IPC分类号： H03K19/0952 , H02M7/537 , H03K17/06 , H03K17/22 , H03K5/19 , H03K19/017
CPC分类号： H03K19/0952 , H02M7/537 , H03K5/19 , H03K17/063 , H03K17/223 , H03K19/01707
摘要： A gate driver includes a drive signal input terminal, a drive signal output terminal, a gate drive circuit, and a serial communication interface. The drive signal input terminal is configured to receive a gate drive signal. The gate drive circuit is coupled to the drive signal input terminal and the drive signal output terminal. The gate drive circuit is configured to provide the gate drive signal to the drive signal output terminal. The serial communication interface is coupled to the drive signal input terminal.
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公开(公告)号：US20170317638A1
公开(公告)日：2017-11-02
申请号：US15143030
申请日：2016-04-29
CPC分类号： H02P31/00 , B60L3/00 , G06F1/28 , H02H7/0844 , H02H7/09
摘要： An apparatus includes a control circuit that includes a configuration register and configured to receive a configuration setting across an external bus. The configuration setting encodes a first voltage state for the apparatus. The control circuit includes an input configured to be coupled to an external electrical device. The control circuit is configured to determine a value of the external device that maps to a second voltage state for the apparatus. The control logic is configured to transition the apparatus to a safe mode upon a determination that the first voltage state does not match the second voltage state.
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