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公开(公告)号：US12216934B2
公开(公告)日：2025-02-04
申请号：US18585619
申请日：2024-02-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriramakrishnan Govindarajan , Mihir Mody
Abstract: Various systems and circuits are provided. One such system includes input interfaces to receive items of input data of different types; output interfaces, each of a different type; an interconnect coupled to the input interfaces and to the output interfaces; and an multichip hub that includes buffers respectively corresponding to the types of input data, context memory blocks, and a data movement engine with a context mapper to determine a context of each item of input data received and provide the item of input data to a corresponding context memory block. Multiple processing blocks within the multichip hub are each configured to perform a respective processing operation. The data movement engine receives context configuration data to determine, for each item of input data received, which of the multiple processing operations are to be applied to the item of input data.
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公开(公告)号：US11798128B2
公开(公告)日：2023-10-24
申请号：US16745589
申请日：2020-01-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Brian Okchon Chae , Niraj Nandan , Anthony Joseph Lell , Mihir Mody
CPC classification number: G06T3/4023 , G06V10/32 , G06V10/96 , G06V10/993 , H04N1/00005 , H04N1/00021 , H04N1/00034 , H04N1/00082 , G06T2207/10016
Abstract: An image data frame is received from an external source. An error concealment operation is performed on the received image data frame in response to determining that a first frame size of the received image data frame is erroneous. The first frame size of the image data frame is determined to be erroneous based on at least one frame synchronization signal associated with the image data frame. An image processing operation is performed on the received image data frame on which the error concealment operation has been performed, thereby enabling an image processing module to perform the image processing operation without entering into a deadlock state and thereby prevent a host processor from having to execute hardware resets of deadlocked modules.
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公开(公告)号：US20230251793A1
公开(公告)日：2023-08-10
申请号：US17668052
申请日：2022-02-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriramakrishnan Govindarajan , Mihir Mody
CPC classification number: G06F3/0656 , G06F3/0604 , G06F3/0679 , G06F13/28 , G06F2213/28
Abstract: An integrated circuit is presented. The integrated circuit has a set of sensor input interfaces and an output interface. The integrated circuit further has a memory with a first and second memory locations. The integrated circuit further has a multi-chip hub module which has a transaction buffer with both a real-time and a non-real-time buffer. The multi-chip hub module has a context mapper, a re-formatter module and an error handling module. The context mapper is configured to map data to the first or second memory location. The multi-chip hub module is configured to process data through the modules and provide processed data to the output interface.
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公开(公告)号：US11144417B2
公开(公告)日：2021-10-12
申请号：US16236745
申请日：2018-12-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Niraj Nandan , Hetul Sanghvi , Mihir Mody , Gary Cooper , Anthony Lell
Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.
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公开(公告)号：US10818067B1
公开(公告)日：2020-10-27
申请号：US16428485
申请日：2019-05-31
Applicant: Texas Instruments Incorporated
Inventor： Mihir Mody , Hemant Hariyani , Anand Balagopalakrishnan , Jason Jones , Ajay Jayaraj , Manoj Koul
Abstract: A method and system for dynamically transferring graphical image processing operations from a graphical processing unit (GPU) to a digital signal processor (DSP). The method includes estimating the number of operations needed for the processing a set of image data; determining the operational limits of a GPU and compare with estimated number of operations and if the operational limits are exceeded; transfer the processing operations to the DSP from the GPU. The transfer can include transferring a portion of executable code for performing the processing operations, and generating a replacement code for the GPU. The DSP can then process a portion of the image data before sending it to the GPU for further processing.
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Patent Agency Ranking
公开(公告)号：US20200210301A1
公开(公告)日：2020-07-02
申请号：US16236745
申请日：2018-12-31
Applicant: Texas Instruments Incorporated
Inventor： NIRAJ NANDAN , Hetul Sanghvi , Mihir Mody , Gary Cooper , Anthony Lell
IPC: G06F11/273 , G06F11/22 , G06F13/16 , G06F13/28 , G06F9/48
Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.
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公开(公告)号：US10325174B2
公开(公告)日：2019-06-18
申请号：US15707695
申请日：2017-09-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Anish Reghunath , Hetul Sanghvi , Michael Lachmayr , Mihir Mody
Abstract: Systems and methods for performing Census Transforms that includes an input from an image, with a support window created within the image, and a kernel within the support window. The Census Transform calculations and comparisons are performed within the kernel windows. One disclosed method allows for previously performed comparison to be calculated and compared as an if not equal invert or if equal use pervious comparison hardware design. Alternatively, a new Census Transform is disclosed which always inverts a previously made comparison. This new approach can be demonstrated to be equivalent to, applying the original Census Transform, on a pre-processed input kernel, where the pre-processing step adds a fractional position index to each pixel within the N×N kernel. The fractional positional index ensures that no two pixels are equal to one another, and thereby makes the Original Census algorithm on pre-processed kernel same as the new Census algorithm on original kernel. The hardware design for this new Census Transform kernel allows for an always invert of previous comparison system resulting in reduced hardware and power consumption.
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公开(公告)号：US09430393B2
公开(公告)日：2016-08-30
申请号：US14583020
申请日：2014-12-24
Applicant: Texas Instruments Incorporated
Inventor： Prashant Dinkar Karandikar , Mihir Mody , Hetul Sanghavi , Vasant Easwaran , Prithvi Y. A. Shankar , Rahul Gulati , Niraj Nandan , Subrangshu Das
CPC classification number: G06F12/0862 , G06F3/06 , G06F12/08 , G06F12/0888 , G06F2212/601 , G06F2212/602
Abstract: A system includes first and second processing components, a qualified based splitter component, a first and second configurable cache element and an arbiter component. The first data processing component generates a first request for a first portion of data at a first location within a memory. The second data processing component generates a second request for a second portion of data at a second location within the memory. The qualifier based splitter component routes the first request and the second request based on a qualifier. The first configurable cache element enables or disables prefetching data within a first region of the memory. The second configurable cache element enables or disables prefetching data within a second region of the memory. The arbiter component routes the first request and the second request to the memory.
Abstract translation: 系统包括第一和第二处理组件，基于限定的分离器组件，第一和第二可配置高速缓存元件和仲裁器组件。 第一数据处理组件在存储器内的第一位置处生成对数据的第一部分的第一请求。 第二数据处理组件在存储器内的第二位置产生第二数据部分的第二请求。 基于限定符的分离器组件基于限定符路由第一请求和第二请求。 第一可配置缓存元件启用或禁用在存储器的第一区域内的预取数据。 第二可配置高速缓存元件在存储器的第二区域内启用或禁用预取数据。 仲裁器组件将第一个请求和第二个请求路由到内存。
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公开(公告)号：US20150003520A1
公开(公告)日：2015-01-01
申请号：US14315742
申请日：2014-06-26
Applicant: Texas Instruments Incorporated
Inventor： Mihir Mody
CPC classification number: H04N19/436 , H04N19/119 , H04N19/156 , H04N19/174 , H04N19/423 , H04N19/82
Abstract: The disclosure provides a video encoder. The video encoder receives a frame and divides the frame into a plurality of tiles. The video encoder includes a plurality of video processing engines communicatively coupled with each other. Each video processing engine receives a tile of the plurality of tiles. A height of each tile is equal to a height of the frame and each tile comprises a plurality of rows. The plurality of video processing engines includes a first and a second video processing engine. The second video processing engine being initiated after the first video processing engines processes M rows of the plurality of rows of the tile, where M is an integer.
Abstract translation: 本公开提供一种视频编码器。 视频编码器接收帧并将帧划分成多个瓦片。 视频编码器包括彼此通信耦合的多个视频处理引擎。 每个视频处理引擎接收多个瓦片的瓦片。 每个瓦片的高度等于该框架的高度，并且每个瓦片包括多个行。 多个视频处理引擎包括第一和第二视频处理引擎。 第一视频处理引擎在第一视频处理引擎处理多个瓦片的行中的M行之后启动的第二视频处理引擎，其中M是整数。
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公开(公告)号：US20240427716A1
公开(公告)日：2024-12-26
申请号：US18816201
申请日：2024-08-27
Applicant: Texas Instruments Incorporated
Inventor： Niraj Nandan , Rajasekhar Reddy Allu , Brian Chae , Mihir Mody
Abstract: Systems and methods enable data aggregation and pattern adaptation in hardware acceleration subsystems. In an example, a system, which may be a hardware thread scheduling system, includes schedulers, each associated with a pattern adapter; hardware accelerators respectively coupled to the schedulers; load store engines respectively associated with the hardware accelerators; a memory coupled to the load store engines; and a direct memory access (DMA) circuit coupled to the memory. Each pattern adapter is able to convert data from one format to another, and each load store engine is able to aggregate data elements to form larger data elements to improve overall processing efficiency.
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