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公开(公告)号：US20150339234A1
公开(公告)日：2015-11-26
申请号：US14583020
申请日：2014-12-24
Applicant: Texas Instruments Incorporated
Inventor： Prashant Dinkar Karandikar , Mihir Mody , Hetul Sanghavi , Vasant Easwaran , Prithvi Y.A. Shankar , Rahul Gulati , Niraj Nandan , Subrangshu Das
IPC: G06F12/08
CPC classification number: G06F12/0862 , G06F3/06 , G06F12/08 , G06F12/0888 , G06F2212/601 , G06F2212/602
Abstract: A system includes first and second processing components, a qualified based splitter component, a first and second configurable cache element and an arbiter component. The first data processing component generates a first request for a first portion of data at a first location within a memory. The second data processing component generates a second request for a second portion of data at a second location within the memory. The qualifier based splitter component routes the first request and the second request based on a qualifier. The first configurable cache element enables or disables prefetching data within a first region of the memory. The second configurable cache element enables or disables prefetching data within a second region of the memory. The arbiter component routes the first request and the second request to the memory.
Abstract translation: 系统包括第一和第二处理组件，基于限定的分离器组件，第一和第二可配置高速缓存元件和仲裁器组件。 第一数据处理组件在存储器内的第一位置处生成对数据的第一部分的第一请求。 第二数据处理组件在存储器内的第二位置产生第二数据部分的第二请求。 基于限定符的分离器组件基于限定符路由第一请求和第二请求。 第一可配置缓存元件启用或禁用在存储器的第一区域内的预取数据。 第二可配置高速缓存元件在存储器的第二区域内启用或禁用预取数据。 仲裁器组件将第一个请求和第二个请求路由到内存。
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公开(公告)号：US09430393B2
公开(公告)日：2016-08-30
申请号：US14583020
申请日：2014-12-24
Applicant: Texas Instruments Incorporated
Inventor： Prashant Dinkar Karandikar , Mihir Mody , Hetul Sanghavi , Vasant Easwaran , Prithvi Y. A. Shankar , Rahul Gulati , Niraj Nandan , Subrangshu Das
CPC classification number: G06F12/0862 , G06F3/06 , G06F12/08 , G06F12/0888 , G06F2212/601 , G06F2212/602
Abstract: A system includes first and second processing components, a qualified based splitter component, a first and second configurable cache element and an arbiter component. The first data processing component generates a first request for a first portion of data at a first location within a memory. The second data processing component generates a second request for a second portion of data at a second location within the memory. The qualifier based splitter component routes the first request and the second request based on a qualifier. The first configurable cache element enables or disables prefetching data within a first region of the memory. The second configurable cache element enables or disables prefetching data within a second region of the memory. The arbiter component routes the first request and the second request to the memory.
Abstract translation: 系统包括第一和第二处理组件，基于限定的分离器组件，第一和第二可配置高速缓存元件和仲裁器组件。 第一数据处理组件在存储器内的第一位置处生成对数据的第一部分的第一请求。 第二数据处理组件在存储器内的第二位置产生第二数据部分的第二请求。 基于限定符的分离器组件基于限定符路由第一请求和第二请求。 第一可配置缓存元件启用或禁用在存储器的第一区域内的预取数据。 第二可配置高速缓存元件在存储器的第二区域内启用或禁用预取数据。 仲裁器组件将第一个请求和第二个请求路由到内存。
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公开(公告)号：US09538092B2
公开(公告)日：2017-01-03
申请号：US14599201
申请日：2015-01-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra Mody , Niraj Nandan , Hetul Sanghavi , Rajsekhar Allu
CPC classification number: H04N5/2355 , H04N5/345 , H04N5/35581
Abstract: Methods and apparatus to generate wide dynamic range images are disclosed. An example apparatus includes a first processing block having first input, second input to receive input data from an image sensor, and first output; a second processing block having third input, fourth input to receive input data from the image sensor, and second output, at least one of the first and second outputs to output a WDR image based on at least two of the first, second, third and fourth inputs; an architecture recognizer having fifth input and third output, the third output to convey an architecture type of the image sensor; a function selector having fourth output to identify at least one of the first and second processing blocks based on the third output; and a sensor adapter having seventh input coupled to the fourth output and having fifth output coupled to the first and third inputs.
Abstract translation: 公开了产生宽动态范围图像的方法和装置。 示例性装置包括具有第一输入的第一处理块，用于从图像传感器接收输入数据的第二输入和第一输出; 具有第三输入的第二处理块，用于接收来自图像传感器的输入数据的第四输入，以及第二输出，第一和第二输出中的至少一个输出，基于第一，第二，第三和第三输入中的至少两个，输出WDR图像; 第四输入; 具有第五输入和第三输出的架构识别器，用于传送图像传感器的架构类型的第三输出; 功能选择器，具有第四输出，用于基于第三输出来识别第一和第二处理块中的至少一个; 以及传感器适配器，其具有耦合到第四输出的第七输入端，并具有耦合到第一和第三输入端的第五输出端。
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公开(公告)号：US20150207974A1
公开(公告)日：2015-07-23
申请号：US14599201
申请日：2015-01-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra Mody , Niraj Nandan , Hetul Sanghavi , Rajsekhar Allu
IPC: H04N5/235 , H04N5/374 , H04N5/3725 , H04N5/355 , H04N5/357
CPC classification number: H04N5/2355 , H04N5/345 , H04N5/35581
Abstract: Methods and apparatus to generate wide dynamic range images are disclosed. An example apparatus includes a first processing block having first input, second input to receive input data from an image sensor, and first output; a second processing block having third input, fourth input to receive input data from the image sensor, and second output, at least one of the first and second outputs to output a WDR image based on at least two of the first, second, third and fourth inputs; an architecture recognizer having fifth input and third output, the third output to convey an architecture type of the image sensor; a function selector having fourth output to identify at least one of the first and second processing blocks based on the third output; and a sensor adapter having seventh input coupled to the fourth output and having fifth output coupled to the first and third inputs.
Abstract translation: 公开了产生宽动态范围图像的方法和装置。 示例性装置包括具有第一输入的第一处理块，用于从图像传感器接收输入数据的第二输入和第一输出; 具有第三输入的第二处理块，用于接收来自图像传感器的输入数据的第四输入，以及第二输出，第一和第二输出中的至少一个输出，基于第一，第二，第三和第三输入中的至少两个，输出WDR图像; 第四输入; 具有第五输入和第三输出的架构识别器，用于传送图像传感器的架构类型的第三输出; 功能选择器，具有第四输出，用于基于第三输出来识别第一和第二处理块中的至少一个; 以及传感器适配器，其具有耦合到第四输出的第七输入端，并具有耦合到第一和第三输入端的第五输出端。
