-
公开(公告)号：US12105653B2
公开(公告)日：2024-10-01
申请号：US18190242
申请日：2023-03-27
Applicant: Texas Instruments Incorporated
Inventor： Niraj Nandan , Rajasekhar Reddy Allu , Brian Chae , Mihir Mody
CPC classification number: G06F13/28 , G06F9/4881 , G06F13/1673 , G06F13/4027 , G06F2213/0038
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed herein to enable data aggregation and pattern adaptation in hardware acceleration subsystems. In some examples, a hardware acceleration subsystem includes a first scheduler, a first hardware accelerator coupled to the first scheduler to process at least a first data element and a second data element, and a first load store engine coupled to the first hardware accelerator, the first load store engine configured to communicate with the first scheduler at a superblock level by sending a done signal to the first scheduler in response to determining that a block count is equal to a first BPR value and aggregate the first data element and the second data element based on the first BPR value to generate a first aggregated data element.
-
公开(公告)号：US10747692B2
公开(公告)日：2020-08-18
申请号：US16234508
申请日：2018-12-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Mody , Niraj Nandan , Hetul Sanghvi , Brian Chae , Rajasekhar Reddy Allu , Jason A. T. Jones , Anthony Lell , Anish Reghunath
Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.
-
公开(公告)号：US11341606B2
公开(公告)日：2022-05-24
申请号：US16930543
申请日：2020-07-16
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Brian Chae , Shashank Dabral , Niraj Nandan , Hetul Sanghvi
Abstract: An apparatus for scaling images is provided that includes at least two input ports, a scaling component coupled to the at least two input ports, the scaling component including a plurality of scalers, the scaling component configurable to map any scaler to any input port of the at least two input ports and configurable to map more than one scaler to any input port, and a memory coupled to the at least two input ports and to outputs of the plurality of scalers, the memory configured to store image data for each input port and scaled image data output by the plurality of scalers.
-
公开(公告)号：US20200349671A1
公开(公告)日：2020-11-05
申请号：US16930543
申请日：2020-07-16
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Brian Chae , Shashank Dabral , Niraj Nandan , Hetul Sanghvi
Abstract: An apparatus for scaling images is provided that includes at least two input ports, a scaling component coupled to the at least two input ports, the scaling component including a plurality of scalers, the scaling component configurable to map any scaler to any input port of the at least two input ports and configurable to map more than one scaler to any input port, and a memory coupled to the at least two input ports and to outputs of the plurality of scalers, the memory configured to store image data for each input port and scaled image data output by the plurality of scalers.
-
公开(公告)号：US10755380B2
公开(公告)日：2020-08-25
申请号：US15143491
申请日：2016-04-29
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Brian Chae , Shashank Dabral , Niraj Nandan , Hetul Sanghvi
Abstract: An apparatus for scaling images is provided that includes at least two input ports, a scaling component coupled to the at least two input ports, the scaling component including a plurality of scalers, the scaling component configurable to map any scaler to any input port of the at least two input ports and configurable to map more than one scaler to any input port, and a memory coupled to the at least two input ports and to outputs of the plurality of scalers, the memory configured to store image data for each input port and scaled image data output by the plurality of scalers.
-
Patent Agency Ranking
公开(公告)号：US20220391338A1
公开(公告)日：2022-12-08
申请号：US17887906
申请日：2022-08-15
Applicant: Texas Instruments Incorporated
Inventor： Anish Reghunath , Brian Chae , Jay Scott Salinger , Chunheng Luo
IPC: G06F13/28 , G06F12/1081 , G06F3/14
Abstract: A system includes a display subsystem. The display subsystem includes a shared buffer having allocated portions, each allocated to one of a plurality of display threads, each display thread associated with a display peripheral. The display subsystem also includes a direct memory access (DMA) engine configured to receive a request from a main processor to deallocate an amount of space from a first allocated portion associated with a first display thread. In response to receiving the request, the DMA engine deallocates the amount of space from the first allocated portion and shifts the allocated portions of at least some of other display threads to maintain contiguity of the allocated portions and concatenate free space at an end of the shared buffer.
-
公开(公告)号：US11237991B2
公开(公告)日：2022-02-01
申请号：US16995364
申请日：2020-08-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Mody , Niraj Nandan , Hetul Sanghvi , Brian Chae , Rajasekhar Reddy Allu , Jason A. T. Jones , Anthony Lell , Anish Reghunath
Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.
-
公开(公告)号：US20210136358A1
公开(公告)日：2021-05-06
申请号：US16669138
申请日：2019-10-30
Applicant: Texas Instruments Incorporated
Inventor： Niraj Nandan , Brian Chae , Mihir Mody , Rajasekhar Reddy Allu
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for image frame freeze detection. An example hardware accelerator includes a core logic circuit to generate second image data based on first image data associated with a first image frame, the second image data corresponding to at least one of processed image data, transformed image data, or one or more image data statistics, a load/store engine (LSE) coupled to the core logic circuit, the LSE to determine a first CRC value based on the second image data obtained from the core logic circuit, and a first interface coupled to a second interface, the second interface coupled to memory, the first interface to transmit the first CRC value obtained from the memory to a host device.
-
公开(公告)号：US20200210360A1
公开(公告)日：2020-07-02
申请号：US16704820
申请日：2019-12-05
Applicant: Texas Instruments Incorporated
Inventor： Anish Reghunath , Brian Chae , Jay Scott Salinger , Chunheng Luo
IPC: G06F13/28 , G06F3/14 , G06F12/1081
Abstract: A system includes a display subsystem. The display subsystem includes a shared buffer having allocated portions, each allocated to one of a plurality of display threads, each display thread associated with a display peripheral. The display subsystem also includes a direct memory access (DMA) engine configured to receive a request from a main processor to deallocate an amount of space from a first allocated portion associated with a first display thread. In response to receiving the request, the DMA engine deallocates the amount of space from the first allocated portion and shifts the allocated portions of at least some of other display threads to maintain contiguity of the allocated portions and concatenate free space at an end of the shared buffer.
-
公开(公告)号：US20170132754A1
公开(公告)日：2017-05-11
申请号：US15143491
申请日：2016-04-29
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Brian Chae , Shashank Dabral , Niraj Nandan , Hetul Sanghvi
Abstract: An apparatus for scaling images is provided that includes at least two input ports, a scaling component coupled to the at least two input ports, the scaling component including a plurality of scalers, the scaling component configurable to map any scaler to any input port of the at least two input ports and configurable to map more than one scaler to any input port, and a memory coupled to the at least two input ports and to outputs of the plurality of scalers, the memory configured to store image data for each input port and scaled image data output by the plurality of scalers.
-
-
-
-
-
-
-
-
-
Search Results
20
records
(took 0.019 seconds)
