-
公开(公告)号：US20250030436A1
公开(公告)日：2025-01-23
申请号：US18399223
申请日：2023-12-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Anand SUBRAMANIAN , Tanmay HALDER , Deepa NAIR J S , Sreeja CHAKINGAL
IPC: H03M3/00
Abstract: In a described example, a circuit includes a digital-to-analog converter (DAC) unit element switch circuit including first and second sign switch inputs, first and second select switch inputs, and first, second and third DAC outputs. Synchronizer logic includes a selection input and first and second synchronization outputs, in which the first synchronization output is coupled to the first select switch input and the second synchronization output is coupled to the second select switch input. Selection logic includes a data input, a sign control output and a selection control output, in which the sign control output is coupled to the first and second sign switch inputs, and the selection control output is coupled to the selection input.
-
公开(公告)号：US20170068265A1
公开(公告)日：2017-03-09
申请号：US15259368
申请日：2016-09-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Anand SUBRAMANIAN , Anand KANNAN , Sunil RAFEEQUE , Venakatesh GUDURI
CPC classification number: G05F1/575
Abstract: A reference circuit may include a bandgap reference stage, a filter stage, and a buffer stage. The reference stage may be configured to generate a reference voltage or current. The filter stage may be coupled to the reference stage and may be configured to receive the reference voltage or current, filter noise from the reference voltage or current, receive a buffer output voltage or current, and filter noise from the buffer output voltage or current. The buffer stage may be coupled to the filter stage and may be configured to isolate the reference stage and the filter stage from a loading effect of a load circuit and generate a reference signal based on the reference voltage or current to drive the load circuit.
Abstract translation: 参考电路可以包括带隙基准级，滤波级和缓冲级。 参考级可以被配置为产生参考电压或电流。 滤波器级可以耦合到参考级，并且可以被配置为从参考电压或电流接收参考电压或电流，滤波器噪声，接收缓冲器输出电压或电流，以及从缓冲器输出电压或电流滤除噪声。 缓冲级可以耦合到滤波器级，并且可以被配置为将参考级和滤波级与负载电路的负载效应隔离，并且基于参考电压或电流产生参考信号以驱动负载电路。
-
公开(公告)号：US20250030391A1
公开(公告)日：2025-01-23
申请号：US18590280
申请日：2024-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Laxmi Vivek TRIPURARI , Anand SUBRAMANIAN , Tanmay HALDER , Anand KANNAN , Priyanshu PANDEY
Abstract: In some examples, a circuit includes a first transistor having a control terminal and first and second terminals. The circuit also includes a first capacitor having first and second terminals, the first terminal of the first capacitor coupled to the control terminal of the first transistor and the second terminal of the first capacitor coupled to the second terminal of the first transistor. The circuit also includes a first switch having first and second terminals, the second terminal of the first switch coupled to the control terminal of the first transistor. The circuit also includes a second capacitor having first and second terminals, the first terminal of the second capacitor coupled to the first terminal of the first transistor and the second terminal of the second capacitor coupled to the first terminal of the first switch.
-
Patent Agency Ranking
公开(公告)号：US20210044267A1
公开(公告)日：2021-02-11
申请号：US16789540
申请日：2020-02-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Anand SUBRAMANIAN , Tanmay HALDER , Anand KANNAN
Abstract: A circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front end (AFE) having an AFE input and an AFE output. The AFE output is coupled the ADC's input. The AFE includes a programmable gain amplifier (PGA) having a first PGA input and a second PGA input. The PGA includes a first operational amplifier (OP AMP) with first and second OPAMP inputs. The AFE also including a programmable resistance circuit having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit includes a resistor network having first and second balance resistances. The first balance resistance is coupled to the first and second OP AMP inputs, and the second balance resistance is coupled to the first and second OP AMP inputs.
-
公开(公告)号：US20200336118A1
公开(公告)日：2020-10-22
申请号：US16574231
申请日：2019-09-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sovan GHOSH , Amal KUMAR KUNDU , Laxmi Vivek TRIPURARI , Anand SUBRAMANIAN
Abstract: A circuit includes first and second gain stages and an output transistor. The second gain stage includes a transconductance amplifier and a variable impedance circuit coupled to an output of the transconductance amplifier. The variable impedance circuit is configured to implement a first impedance level at frequencies below a first frequency threshold and to implement a second impedance level at frequencies above a second frequency level. The first impedance level is larger than the second impedance level. The output transistor has a control input coupled to the variable impedance circuit. At frequencies above the second frequency threshold, the second impedance level is configured to be inversely related to current through the output transistor.
-
公开(公告)号：US20200304139A1
公开(公告)日：2020-09-24
申请号：US16661456
申请日：2019-10-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Uttam Kumar AGARWAL , Anand KANNAN , Ramamurthy VISHWESHWARA , Anand SUBRAMANIAN , Pedro Ramon GELABERT , Diljith Mathal THODI , Abhijit Anant PATKI
Abstract: A circuit includes a programmable gain amplifier (PGA) having a PGA output. The circuit further includes a delta-sigma modulator having an input coupled to the PGA output. The circuit also includes a digital filter and a dynamic range enhancer (DRE) circuit. The digital filter is coupled to the delta-sigma modulator output. The DRE circuit is coupled to the delta-sigma modulator output and to the PGA. The DRE circuit is configured to monitor a signal level of the delta-sigma modulator output. Responsive to the signal level being less than a DRE threshold, the DRE circuit is configured to program the PGA for a gain level greater than unity gain and to cause the digital filter to implement an attenuation of a same magnitude as the gain level to be programmed into the PGA.
-
公开(公告)号：US20250030431A1
公开(公告)日：2025-01-23
申请号：US18496436
申请日：2023-10-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Tanmay HALDER , Anand SUBRAMANIAN , Anand KANNAN
IPC: H03M1/08
Abstract: In some examples, a circuit includes a first integrator having an input and an output. The circuit also includes a switching architecture having first and second terminals, the first terminal of the switching architecture coupled to the output of the first integrator. The circuit also includes a second integrator having an input and an output, the input of the second integrator coupled to the second terminal of the switching architecture. The circuit also includes a quantizer having an input and an output, the input of the quantizer coupled to the output of the second integrator. The circuit also includes a digital processing circuit having an input and an output, the input of the digital processing circuit coupled to the output of the quantizer.
-
公开(公告)号：US20210006211A1
公开(公告)日：2021-01-07
申请号：US17027093
申请日：2020-09-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sovan GHOSH , Amal KUMAR KUNDU , Laxmi Vivek TRIPURARI , Anand SUBRAMANIAN
Abstract: A circuit includes first and second gain stages and an output transistor. The second gain stage includes a transconductance amplifier and a variable impedance circuit coupled to an output of the transconductance amplifier. The variable impedance circuit is configured to implement a first impedance level at frequencies below a first frequency threshold and to implement a second impedance level at frequencies above a second frequency level. The first impedance level is larger than the second impedance level. The output transistor has a control input coupled to the variable impedance circuit. At frequencies above the second frequency threshold, the second impedance level is configured to be inversely related to current through the output transistor.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.012 seconds)
