公开(公告)号：US09734271B2

公开(公告)日：2017-08-15

申请号：US14965661

申请日：2015-12-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yu Ching Lee ,  Jian-Hong Lin ,  Te-Liang Lee ,  Jyh-Weei Hsia

IPC: H01L27/10 ,  H01L29/73 ,  G06F17/50 ,  H01L27/06 ,  H01L23/535 ,  H01L29/861 ,  H01L29/423

CPC classification number: G06F17/5045 ,  G06F17/5081 ,  G06F2217/76 ,  H01L23/535 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/861 ,  H01L29/8613

Abstract: In some embodiments, in a method for a semiconductor device having an interconnect structure, a design layout is received. A metal line in the design layout is identified, which has at least one via thereon and does not couple downward with an oxide diffusion region. The area of a gate oxide coupled with the metal line is obtained from the design layout. The method comprises determining whether the area of the gate oxide is greater than a first predetermined value. When the area of the gate oxide is greater than the first predetermined value, a charge release path is coupled with the metal line.