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公开(公告)号：US09176396B2
公开(公告)日：2015-11-03
申请号：US13778386
申请日：2013-02-27
发明人： Yung-Yao Lee , Ying-Ying Wang
CPC分类号： G03F7/70633 , G01B11/14
摘要： One embodiment relates to a method for overlay sampling. The method provides a number of fields over a semiconductor wafer surface. An inner subgroup of the number of fields includes fields in a central region of the wafer surface. An outer subgroup of the number of fields includes neighboring fields near a circumferential edge of the wafer surface. The method measures a first number of overlay conditions at a corresponding first number of overlay structures within a field of the inner subgroup. The method also measures a second number of overlay conditions at a corresponding second number of overlay structures within a field of the outer subgroup. The second number is greater than the first number. Based on the measured first number of overlay conditions and the measured second number of overlay conditions, the method determines an alignment condition for two or more layers on the semiconductor wafer surface.
摘要翻译： 一个实施例涉及用于重叠采样的方法。 该方法提供半导体晶片表面上的多个场。 场数的内部子组包括在晶片表面的中心区域中的场。 多个场的外部子组包括在晶片表面的周边附近的相邻的场。 该方法测量在内部子组的字段内的对应的第一数量的覆盖结构的第一数量的覆盖条件。 该方法还在外部子组的字段内的对应的第二数量的覆盖结构处测量第二数量的覆盖条件。 第二个数字大于第一个数字。 基于测量的第一数量的覆盖条件和所测量的第二覆盖条件数，该方法确定半导体晶片表面上的两层或更多层的取向条件。
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公开(公告)号：US10747128B2
公开(公告)日：2020-08-18
申请号：US15906580
申请日：2018-02-27
发明人： Yung-Yao Lee , Heng-Hsin Liu , Hung-Ming Kuo , Jui-Chun Peng
IPC分类号： G03F9/00 , G03F7/20 , H01L21/67 , H01L21/027 , H01L21/66
摘要： In a method executed in an exposure apparatus, a focus control effective region and a focus control exclusion region are set based on an exposure map and a chip area layout within an exposure area. Focus-leveling data are measured over a wafer. A photo resist layer on the wafer is exposed with an exposure light. When a chip area of a plurality of chip areas of the exposure area is located within an effective region of a wafer, the chip area is included in the focus control effective region, and when a part of or all of a chip area of the plurality of chip areas is located on or outside a periphery of the effective region of the wafer, the chip area is included in the focus control exclusion region In the exposing, a focus-leveling is controlled by using the focus-leveling data measured at the focus control effective region.
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公开(公告)号：US20170235233A1
公开(公告)日：2017-08-17
申请号：US15413737
申请日：2017-01-24
发明人： Yung-Yao Lee , Yi-Ping Hsieh
IPC分类号： G03F7/20
CPC分类号： G03F7/70633 , G03F9/7003
摘要： A method for layoutless overlay control is provided. In some embodiments, a target layer covering a workpiece is patterned using a reticle. The patterning forms a plurality of exposure fields arranged according to a first exposure field layout. Alignment of the exposure fields relative to the workpiece is measured to generate displacement vectors. An inter-field model and an intra-field model are trained using the displacement vectors and a reference field layout. The intra-field model is transformed for use with a second exposure field layout, where the second exposure field layout is different than the first exposure field layout. Overlay corrections are generated based on the trained inter-field model and the transformed intra-field model.
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公开(公告)号：US11035619B2
公开(公告)日：2021-06-15
申请号：US15472428
申请日：2017-03-29
发明人： Wei-Chang Cheng , Chi-Hung Liao , Chien-Hung Wang , Guan-Yu Lin , Yung-Yao Lee
摘要： A drainage device includes a tank, a pipe and an air duct. The tank has a base plate and at least one first wall. The first wall is disposed on the base plate. The base plate and the first wall define a space. The pipe defines a channel. The pipe connects with the base plate. The channel communicates with the space. The air duct is disposed partially in the space and partially in the channel. There exists at least one gap between an outer surface of the air duct and an inner surface of the pipe.
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公开(公告)号：US10061215B2
公开(公告)日：2018-08-28
申请号：US15182348
申请日：2016-06-14
发明人： Yung-Yao Lee , Jui-Chun Peng , Ho-Ping Chen , Heng-Hsin Liu
IPC分类号： G03F9/00
CPC分类号： G03F9/7034 , G03F9/7084 , G03F9/7088
摘要： In a method for fabricating a resist pattern, a substrate coated with a photo resist is loaded on a stage of an exposure apparatus. Underlying patterns are fabricated on the substrate. A surface slope of an exposure area on the substrate is measured. An alignment measurement is performed by detecting an alignment pattern formed in the underlying patterns. An alignment measurement result is corrected based on the measured surface slope. The substrate is aligned to a photo mask by using the corrected alignment measurement result. The photo resist is exposed to radiation passing through the photo mask to form patterns.
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公开(公告)号：US20180164839A1
公开(公告)日：2018-06-14
申请号：US15472428
申请日：2017-03-29
发明人： Wei-Chang Cheng , Chi-Hung Liao , Chien-Hung Wang , Guan-Yu Lin , Yung-Yao Lee
CPC分类号： F28D15/0266 , F25D21/14 , F28D15/025 , G05D23/00 , Y02B30/765
摘要： A drainage device includes a tank, a pipe and an air duct. The tank has a base plate and at least one first wall. The first wall is disposed on the base plate. The base plate and the first wall define a space. The pipe defines a channel. The pipe connects with the base plate. The channel communicates with the space. The air duct is disposed partially in the space and partially in the channel. There exists at least one gap between an outer surface of the air duct and an inner surface of the pipe.
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公开(公告)号：US09766559B2
公开(公告)日：2017-09-19
申请号：US14066949
申请日：2013-10-30
发明人： Yung-Yao Lee , Ying-Ying Wang , Yi-Ping Hsieh , Heng-Hsin Liu
IPC分类号： G03F9/00
CPC分类号： G03F9/7084 , G03F9/70 , G03F9/7007 , G03F9/7046 , G03F9/7088 , G03F2009/005
摘要： An edge-dominant alignment method for use in an exposure scanner system is provided. The method includes the steps of: providing a wafer having a plurality of shot areas, wherein each shot area has a plurality of alignment marks; determining a first outer zone of the wafer, wherein the first outer zone includes a first portion of the shot areas along a first outer edge of the wafer; determining a scan path according to the shot areas of the first outer zone; and performing an aligning process to each shot area of the first outer zone according to the scan path and an alignment mark of each shot area of the first outer zone.
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公开(公告)号：US10061211B2
公开(公告)日：2018-08-28
申请号：US15413737
申请日：2017-01-24
发明人： Yung-Yao Lee , Yi-Ping Hsieh
CPC分类号： G03F7/70633 , G03F9/7003
摘要： A method for layoutless overlay control is provided. In some embodiments, a target layer covering a workpiece is patterned using a reticle. The patterning forms a plurality of exposure fields arranged according to a first exposure field layout. Alignment of the exposure fields relative to the workpiece is measured to generate displacement vectors. An inter-field model and an intra-field model are trained using the displacement vectors and a reference field layout. The intra-field model is transformed for use with a second exposure field layout, where the second exposure field layout is different than the first exposure field layout. Overlay corrections are generated based on the trained inter-field model and the transformed intra-field model.
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公开(公告)号：US09927719B2
公开(公告)日：2018-03-27
申请号：US14882493
申请日：2015-10-14
发明人： Yung-Yao Lee , Ying-Ying Wang
CPC分类号： G03F7/70633 , G01B11/14
摘要： One embodiment relates to a method for overlay sampling. The method provides a number of fields over a semiconductor wafer surface. An inner subgroup of the number of fields includes fields in a central region of the wafer surface. An outer subgroup of the number of fields includes neighboring fields near a circumferential edge of the wafer surface. The method measures a first number of overlay conditions at a corresponding first number of overlay structures within a field of the inner subgroup. The method also measures a second number of overlay conditions at a corresponding second number of overlay structures within a field of the outer subgroup. The second number is greater than the first number. Based on the measured first number of overlay conditions and the measured second number of overlay conditions, the method determines an alignment condition for two or more layers on the semiconductor wafer surface.
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公开(公告)号：US09841687B2
公开(公告)日：2017-12-12
申请号：US14798563
申请日：2015-07-14
发明人： Yung-Yao Lee , Heng-Hsin Liu , Jui-Chun Peng , Yung-Cheng Chen
CPC分类号： G03F7/70633
摘要： The present disclosure relates to a method of semiconductor processing. The method includes, receiving a first wafer having a photoresist coating on a face of the first wafer. An exposure unit is used to perform a first number of radiation exposures on the photoresist coating, thereby forming an exposed photoresist coating. The exposed photoresist coating is developed, thereby forming a developed photoresist coating. An OVL measurement zone pattern is selected from a number of different, pre-determined OVL measurement zone patterns based on at least one of: the first number of radiation exposures performed on the first wafer or a previous number of radiation exposures performed on a previously processed wafer, which was processed before the first wafer. A number of OVL measurements are performed on the developed photoresist coating within the selected OVL measurement zone pattern.
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