-
1.发明申请Method for finding maximum volume and minimum cut in a network of interconnected nodes 有权在互联节点网络中查找最大容量和最小值的方法公开(公告)号：US20050235236A1
公开(公告)日：2005-10-20
申请号：US10928627
申请日：2004-08-27
申请人： Sunil Sharma , Ajay Tomar , Dhabalendu Samanta
发明人： Sunil Sharma , Ajay Tomar , Dhabalendu Samanta
CPC分类号： G06F17/5054
摘要： A method for finding a maximum volume and minimum cutset in a network of interconnected nodes is provided. The method is applicable to systems that can be reduced to such a network, including telecommunication networks, traffic networks, computer networks, layouts, hydraulic networks, etc. An equivalent network is derived by replacing all nodes other then the source and sink by two interconnected nodes. A conventional method applies an augmenting path algorithm that identifies a cutset. If the feasible cutset is not achieved then a reduced network is constructed by directly connecting the member nodes of identified cutsets to the source node and repeating the above process for the reduced network until a feasible cutset is achieved.
摘要翻译： 提供了一种用于在互连节点的网络中找到最大容量和最小剪切的方法。 该方法适用于可以减少到这样的网络的系统，包括电信网络，业务网络，计算机网络，布局，液压网络等。通过将所有节点替换为源和汇两个互连的所有节点而导出等效网络 节点。 常规方法应用识别切片的增强路径算法。 如果没有实现可行的切割，则通过将识别的切割器的成员节点直接连接到源节点并且对于减少的网络重复上述过程，直到实现可行的切片来构造缩小的网络。
-
2.发明申请公开(公告)号：US20050039157A1
公开(公告)日：2005-02-17
申请号：US10830862
申请日：2004-04-23
申请人： Sunil Sharma , Ajay Tomar , Dhabalendu Samanta
发明人： Sunil Sharma , Ajay Tomar , Dhabalendu Samanta
CPC分类号： G06F17/5054
摘要： The method for mapping a logic circuit to a plurality of interconnectable, programmable look up tables (LUT) elements includes forming logic element groups including individual logic elements and/or previously formed logic element groups that are capable of being accommodated within the fanin and/or fanout capacity of a target LUT. The method further includes mapping the formed logic element group to the target LUT, and repeating the process for forming logic element groups and mapping to target LUTs for the entire network in a manner such that at each stage only the unmapped logic element/elements and mapped logic element groups of the previous stage are considered for mapping.
摘要翻译： 用于将逻辑电路映射到多个可互连的可编程查询表（LUT）元件的方法包括形成逻辑元件组，其包括单独的逻辑元件和/或先前形成的逻辑元件组，所述逻辑元件组能够被容纳在所述扇形元件内和/或 目标LUT的扇出容量。 该方法还包括将所形成的逻辑元件组映射到目标LUT，并且以这样的方式重复形成逻辑元件组并映射到目标LUT的处理，使得在每个阶段仅将未映射的逻辑元件/元素和映射 考虑前一阶段的逻辑单元组进行映射。
-
公开(公告)号：US20050156626A1
公开(公告)日：2005-07-21
申请号：US11025785
申请日：2004-12-29
申请人： Ajay Tomar , Dhabalendu Samanta
发明人： Ajay Tomar , Dhabalendu Samanta
CPC分类号： G06F17/5054
摘要： A method and system for improved optimal mapping of LUT based FPGA's. The invention comprises performing a topological sort on the network to be mapped, whereby the network is represented in form of a Directed Acyclic Graph. The system locates feasible reconvergent paths existing from transitive fan-ins of each node using a Reconvergent Path Locator for replicating fan-outs of the nodes in the DAG, and therefore optimizing the number of LUT's and the time consumed in the mapping process.
摘要翻译： 一种用于改进基于LUT的FPGA的最佳映射的方法和系统。 本发明包括在要映射的网络上执行拓扑排序，由此网络以定向无循环图的形式表示。 该系统使用一个用于复制DAG中的节点的扇出的再生路径定位器来定位存在于每个节点的传递扇区的可行再映射路径，因此优化LUT的数量和映射过程中消耗的时间。
-
4.发明授权公开(公告)号：US07191427B2
公开(公告)日：2007-03-13
申请号：US10830862
申请日：2004-04-23
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： The method for mapping a logic circuit to a plurality of interconnectable, programmable look up tables (LUT) elements includes forming logic element groups including individual logic elements and/or previously formed logic element groups that are capable of being accommodated within the fanin and/or fanout capacity of a target LUT. The method further includes mapping the formed logic element group to the target LUT, and repeating the process for forming logic element groups and mapping to target LUTs for the entire network in a manner such that at each stage only the unmapped logic element/elements and mapped logic element groups of the previous stage are considered for mapping.
摘要翻译： 用于将逻辑电路映射到多个可互连的可编程查询表（LUT）元件的方法包括形成逻辑元件组，其包括单独的逻辑元件和/或先前形成的逻辑元件组，所述逻辑元件组能够被容纳在所述扇形元件内和/或 目标LUT的扇出容量。 该方法还包括将所形成的逻辑元件组映射到目标LUT，并且以这样的方式重复形成逻辑元件组并映射到目标LUT的处理，使得在每个阶段仅将未映射的逻辑元件/元素和映射 考虑前一阶段的逻辑单元组进行映射。
-
公开(公告)号：US08028262B2
公开(公告)日：2011-09-27
申请号：US12117656
申请日：2008-05-08
申请人： Ajay Tomar , Dhabalendu Samanta
发明人： Ajay Tomar , Dhabalendu Samanta
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Methods and systems improve mapping of LUT based FPGAs. In some embodiments, a topological sort is performed on a network to be mapped, whereby the network is represented as a Directed Acyclic Graph. The system locates feasible reconvergent paths existing from transitive fan-ins of individual nodes using a Reconvergent Path Locator for replicating fan-outs of the nodes in the DAG, and therefore improves the number of LUTs and the time consumed in the mapping process.
摘要翻译： 方法和系统改进了基于LUT的FPGA的映射。 在一些实施例中，在要映射的网络上执行拓扑排序，由此网络被表示为定向非循环图。 系统通过使用用于复制DAG中的节点扇出的重构路径定位器来定位存在于各个节点的传递扇区的可行重新收敛路径，从而提高了LUT的数量和映射过程中消耗的时间。
-
公开(公告)号：US20080209385A1
公开(公告)日：2008-08-28
申请号：US12117656
申请日：2008-05-08
申请人： Ajay Tomar , Dhabalendu Samanta
发明人： Ajay Tomar , Dhabalendu Samanta
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Methods and systems improve mapping of LUT based FPGAs. In some embodiments, a topological sort is performed on a network to be mapped, whereby the network is represented as a Directed Acyclic Graph. The system locates feasible reconvergent paths existing from transitive fan-ins of individual nodes using a Reconvergent Path Locator for replicating fan-outs of the nodes in the DAG, and therefore improves the number of LUTs and the time consumed in the mapping process.
摘要翻译： 方法和系统改进了基于LUT的FPGA的映射。 在一些实施例中，在要映射的网络上执行拓扑排序，由此网络被表示为定向非循环图。 系统通过使用用于复制DAG中的节点扇出的重构路径定位器来定位存在于各个节点的传递扇区的可行重新收敛路径，从而提高了LUT的数量和映射过程中消耗的时间。
-
公开(公告)号：US07415681B2
公开(公告)日：2008-08-19
申请号：US11025785
申请日：2004-12-29
申请人： Ajay Tomar , Dhabalendu Samanta
发明人： Ajay Tomar , Dhabalendu Samanta
IPC分类号： G06F17/50 , G06F9/45 , H03K17/693
CPC分类号： G06F17/5054
摘要： A method and system for improved optimal mapping of LUT based FPGA's. The invention comprises performing a topological sort on the network to be mapped, whereby the network is represented in form of a Directed Acyclic Graph. The system locates feasible reconvergent paths existing from transitive fan-ins of each node using a Reconvergent Path Locator for replicating fan-outs of the nodes in the DAG, and therefore optimizing the number of LUT's and the time consumed in the mapping process.
摘要翻译： 一种用于改进基于LUT的FPGA的最佳映射的方法和系统。 本发明包括在要映射的网络上执行拓扑排序，由此网络以定向无循环图的形式表示。 该系统使用一个用于复制DAG中的节点的扇出的再生路径定位器来定位存在于每个节点的传递扇区的可行再映射路径，因此优化LUT的数量和映射过程中消耗的时间。
-
8.发明授权Method for finding maximum volume and minimum cut in a network of interconnected nodes 有权在互联节点网络中查找最大容量和最小值的方法公开(公告)号：US07188328B2
公开(公告)日：2007-03-06
申请号：US10928627
申请日：2004-08-27
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method for finding a maximum volume and minimum cutset in a network of interconnected nodes is provided. The method is applicable to systems that can be reduced to such a network, including telecommunication networks, traffic networks, computer networks, layouts, hydraulic networks, etc. An equivalent network is derived by replacing all nodes other then the source and sink by two interconnected nodes. A conventional method applies an augmenting path algorithm that identifies a cutset. If the feasible cutset is not achieved then a reduced network is constructed by directly connecting the member nodes of identified cutsets to the source node and repeating the above process for the reduced network until a feasible cutset is achieved.
摘要翻译： 提供了一种用于在互连节点的网络中找到最大容量和最小剪切的方法。 该方法适用于可以减少到这样的网络的系统，包括电信网络，业务网络，计算机网络，布局，液压网络等。通过将所有节点替换为源和汇两个互连的所有节点而导出等效网络 节点。 常规方法应用识别切片的增强路径算法。 如果没有实现可行的切割，则通过将识别的切割器的成员节点直接连接到源节点并且对于减少的网络重复上述过程，直到实现可行的切片来构造缩小的网络。
-
9.发明授权Efficient method for mapping a logic design on field programmable gate arrays 失效用于在现场可编程门阵列上映射逻辑设计的高效方法公开(公告)号：US07676782B2
公开(公告)日：2010-03-09
申请号：US11319015
申请日：2005-12-27
申请人： Dhabalendu Samanta , Viren Agarwal
发明人： Dhabalendu Samanta , Viren Agarwal
CPC分类号： G06F17/5054
摘要： An efficient method for mapping a logic design on Field Programmable Gate Arrays involves a determination of the minimum required square grid of FPGA logic blocks for mapping the design, providing a compensation factor on the minimum square grids, selecting the maximum value among the compensated square grids for reducing the mapping time; and implementing a legalization adjustment to ensure mapping of said compensated design.
摘要翻译： 用于映射现场可编程门阵列的逻辑设计的有效方法涉及确定用于映射设计的FPGA逻辑块的最小所需方格，为最小二乘栅格提供补偿因子，选择补偿方格栅格中的最大值 用于缩短映射时间; 并执行合法化调整，以确保所述补偿设计的映射。
-
10.发明申请Efficient method for mapping a logic design on field programmable gate arrays 失效用于在现场可编程门阵列上映射逻辑设计的高效方法公开(公告)号：US20060190906A1
公开(公告)日：2006-08-24
申请号：US11319015
申请日：2005-12-27
申请人： Dhabalendu Samanta , Viren Agarwal
发明人： Dhabalendu Samanta , Viren Agarwal
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： An efficient method for mapping a logic design on Field Programmable Gate Arrays involves a determination of the minimum required square grid of FPGA logic blocks for mapping the design, providing a compensation factor on the minimum square grids, selecting the maximum value among the compensated square grids for reducing the mapping time; and implementing a legalization adjustment to ensure mapping of said compensated design.
摘要翻译： 用于映射现场可编程门阵列的逻辑设计的有效方法涉及确定用于映射设计的FPGA逻辑块的最小所需方格，为最小二乘栅格提供补偿因子，选择补偿方格栅格中的最大值 用于缩短映射时间; 并执行合法化调整，以确保所述补偿设计的映射。
-
-
-
-
-
-
-
-
-
搜索结果
10 条记录 (耗时 0.025 秒)
