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    Mapping of programmable logic devices
    1.
    再颁专利
    Mapping of programmable logic devices 有权
    可编程逻辑器件的映射

    公开(公告)号：USRE43378E1

    公开(公告)日：2012-05-08

    申请号：US12288359

    申请日：2008-10-17

    申请人： Sunil Kumar Sharma

    发明人： Sunil Kumar Sharma

    IPC分类号： G06F17/50 ,  G06F7/38 ,  H03K19/173

    CPC分类号： G06F17/5054

    摘要： A method for mapping an electronic digital circuit to a Look Up table (LUT) based Programmable Logic Deviceoperates by selecting an unmapped or partially mapped LUT, and identifying a group of circuit elements for mapping on the selected LUT based on the available capacity of the selected LUT and the mapping constraints. The identified circuit elements are mapped onto the selected LUT. The identification of circuit elements and mapping is carried out while taking into consideration the Cascade Logic associated with the selected LUT. The process continues until all circuit elements have been mapped. The group of circuit elements is mapped to the cascade logic prior to mapping on the LUTs. Conversely, the cascade logic is incorporated only after all circuit elements have initially been mapped onto LUTs or some elements remain unmapped after all LUTs have been utilized. The mapping constraints include timing, placement, and size constraints.

    摘要翻译： 一种用于将电子数字电路映射到基于查找表（LUT）的可编程逻辑器件通过选择未映射或部分映射的LUT进行操作的方法，以及基于所选择的可用容量来识别用于在所选择的LUT上进行映射的电路元件组 LUT和映射约束。 所识别的电路元件被映射到所选择的LUT上。 在考虑与所选LUT相关联的级联逻辑时，进行电路元件的识别和映射。 该过程一直持续到所有电路元件都被映射。 在对LUT进行映射之前，将电路元件组映射到级联逻辑。 相反地​​，级联逻辑仅在所有电路元件最初被映射到LUT之后才被并入，或者在所有的LUT被利用之后，某些元件保持未被映射。 映射约束包括时序，位置和大小约束。

    Method for finding maximum volume and minimum cut in a network of interconnected nodes
    2.
    发明授权
    Method for finding maximum volume and minimum cut in a network of interconnected nodes 有权
    在互联节点网络中查找最大容量和最小值的方法

    公开(公告)号：US07188328B2

    公开(公告)日：2007-03-06

    申请号：US10928627

    申请日：2004-08-27

    申请人： Sunil Kumar Sharma ,  Ajay Tomar ,  Dhabalendu Samanta

    发明人： Sunil Kumar Sharma ,  Ajay Tomar ,  Dhabalendu Samanta

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： A method for finding a maximum volume and minimum cutset in a network of interconnected nodes is provided. The method is applicable to systems that can be reduced to such a network, including telecommunication networks, traffic networks, computer networks, layouts, hydraulic networks, etc. An equivalent network is derived by replacing all nodes other then the source and sink by two interconnected nodes. A conventional method applies an augmenting path algorithm that identifies a cutset. If the feasible cutset is not achieved then a reduced network is constructed by directly connecting the member nodes of identified cutsets to the source node and repeating the above process for the reduced network until a feasible cutset is achieved.

    摘要翻译： 提供了一种用于在互连节点的网络中找到最大容量和最小剪切的方法。 该方法适用于可以减少到这样的网络的系统，包括电信网络，业务网络，计算机网络，布局，液压网络等。通过将所有节点替换为源和汇两个互连的所有节点而导出等效网络 节点。 常规方法应用识别切片的增强路径算法。 如果没有实现可行的切割，则通过将识别的切割器的成员节点直接连接到源节点并且对于减少的网络重复上述过程，直到实现可行的切片来构造缩小的网络。

    Method for mapping a logic circuit to a programmable look up table (LUT)
    3.
    发明授权
    Method for mapping a logic circuit to a programmable look up table (LUT) 失效
    将逻辑电路映射到可编程查询表（LUT）的方法

    公开(公告)号：US07191427B2

    公开(公告)日：2007-03-13

    申请号：US10830862

    申请日：2004-04-23

    申请人： Sunil Kumar Sharma ,  Ajay Tomar ,  Dhabalendu Samanta

    发明人： Sunil Kumar Sharma ,  Ajay Tomar ,  Dhabalendu Samanta

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： The method for mapping a logic circuit to a plurality of interconnectable, programmable look up tables (LUT) elements includes forming logic element groups including individual logic elements and/or previously formed logic element groups that are capable of being accommodated within the fanin and/or fanout capacity of a target LUT. The method further includes mapping the formed logic element group to the target LUT, and repeating the process for forming logic element groups and mapping to target LUTs for the entire network in a manner such that at each stage only the unmapped logic element/elements and mapped logic element groups of the previous stage are considered for mapping.

    摘要翻译： 用于将逻辑电路映射到多个可互连的可编程查询表（LUT）元件的方法包括形成逻辑元件组，其包括单独的逻辑元件和/或先前形成的逻辑元件组，所述逻辑元件组能够被容纳在所述扇形元件内和/或 目标LUT的扇出容量。 该方法还包括将所形成的逻辑元件组映射到目标LUT，并且以这样的方式重复形成逻辑元件组并映射到目标LUT的处理，使得在每个阶段仅将未映射的逻辑元件/元素和映射 考虑前一阶段的逻辑单元组进行映射。

    Mapping of programmable logic devices
    4.
    发明授权
    Mapping of programmable logic devices 有权
    可编程逻辑器件的映射

    公开(公告)号：US07124392B2

    公开(公告)日：2006-10-17

    申请号：US10675908

    申请日：2003-09-29

    申请人： Sunil Kumar Sharma

    发明人： Sunil Kumar Sharma

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： A method for mapping an electronic digital circuit to a Look Up table (LUT) based Programmable Logic Deviceoperates by selecting an unmapped or partially mapped LUT, and identifying a group of circuit elements for mapping on the selected LUT based on the available capacity of the selected LUT and the mapping constraints. The identified circuit elements are mapped onto the selected LUT. The identification of circuit elements and mapping is carried out while taking into consideration the Cascade Logic associated with the selected LUT. The process continues until all circuit elements have been mapped. The group of circuit elements is mapped to the cascade logic prior to mapping on the LUTs. Conversely, the cascade logic is incorporated only after all circuit elements have initially been mapped onto LUTs or some elements remain unmapped after all LUTs have been utilized. The mapping constraints include timing, placement, and size constraints.

    摘要翻译： 一种用于将电子数字电路映射到基于查找表（LUT）的可编程逻辑器件通过选择未映射或部分映射的LUT进行操作的方法，以及基于所选择的可用容量来识别用于在所选择的LUT上进行映射的电路元件组 LUT和映射约束。 所识别的电路元件被映射到所选择的LUT上。 在考虑与所选LUT相关联的级联逻辑时，进行电路元件的识别和映射。 该过程一直持续到所有电路元件都被映射为止。 在对LUT进行映射之前，将电路元件组映射到级联逻辑。 相反地​​，级联逻辑仅在所有电路元件最初被映射到LUT之后才被并入，或者在所有的LUT被利用之后，某些元件保持未被映射。 映射约束包括时序，位置和大小约束。