发明申请
- 专利标题： Optimal mapping of LUT based FPGA
- 专利标题（中）： 基于LUT的FPGA的最佳映射
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申请号： US11025785申请日： 2004-12-29
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公开(公告)号： US20050156626A1公开(公告)日： 2005-07-21
- 发明人: Ajay Tomar , Dhabalendu Samanta
- 申请人： Ajay Tomar , Dhabalendu Samanta
- 申请人地址： IN Noida
- 专利权人： STMicroelectronics PVT. LTD.
- 当前专利权人： STMicroelectronics PVT. LTD.
- 当前专利权人地址： IN Noida
- 优先权： IN1639/DEL/2003 20031229
- 主分类号： G06F17/50
- IPC分类号： G06F17/50 ; H03K19/00
摘要：
A method and system for improved optimal mapping of LUT based FPGA's. The invention comprises performing a topological sort on the network to be mapped, whereby the network is represented in form of a Directed Acyclic Graph. The system locates feasible reconvergent paths existing from transitive fan-ins of each node using a Reconvergent Path Locator for replicating fan-outs of the nodes in the DAG, and therefore optimizing the number of LUT's and the time consumed in the mapping process.
公开/授权文献
- US07415681B2 Optimal mapping of LUT based FPGA 公开/授权日：2008-08-19
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