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    Timing operations in an IC with configurable circuits
    3.
    发明授权
    Timing operations in an IC with configurable circuits 有权
    具有可配置电路的IC中的定时操作

    公开(公告)号：US08756547B2

    公开(公告)日：2014-06-17

    申请号：US13430674

    申请日：2012-03-26

    申请人： Steven Teig ,  Andrew Caldwell

    发明人： Steven Teig ,  Andrew Caldwell

    IPC分类号： G06F17/50 ,  H03K19/177

    CPC分类号： G06F17/5081 ,  G06F17/5054 ,  G06F2217/84 ,  H03K19/1731 ,  H03K19/17748

    摘要： Some embodiments provide a method that identifies a first physical design solution for positioning several configurable operations on several reconfigurable circuits of an integrated circuit (IC). The method identifies a second physical design solution for positioning the configurable operations on the configurable circuits. One of the identified physical design solutions has one reconfigurable circuit perform a particular configurable operation in at least two reconfiguration cycles while the other identified solution does not have one reconfigurable circuit perform the particular configurable operation in two reconfiguration cycles. The method costs the first and second physical design solutions. The method selects one of the two physical design solutions based on the costs.

    摘要翻译： 一些实施例提供了一种识别用于在集成电路（IC）的几个可重新配置的电路上定位多个可配置操作的第一物理设计解决方案的方法。 该方法识别用于将可配置操作定位在可配置电路上的第二物理设计解决方案。 所识别的物理设计解决方案之一具有一个可重构电路在至少两个重新配置周期中执行特定的可配置操作，而另一个识别的解决方案没有一个可重配置电路在两个重新配置周期中执行特定的可配置操作。 该方法花费第一和第二物理设计解决方案。 该方法基于成本选择两种物理设计方案之一。

    Operational cycle assignment in a configurable IC
    4.
    发明授权
    Operational cycle assignment in a configurable IC 失效
    可配置IC中的操作周期分配

    公开(公告)号：US08683410B2

    公开(公告)日：2014-03-25

    申请号：US12965815

    申请日：2010-12-10

    申请人： Andre Rohe ,  Steven Teig

    发明人： Andre Rohe ,  Steven Teig

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5054 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17776

    摘要： Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. For at least a first set of operations that has a start operation and an end operation, the method assigns a particular operation in the first set to a first operational cycle based at least partially on the position of the particular operation with respect to the start and end operations.

    摘要翻译： 一些实施例提供了一种用多个可配置电路设计可配置集成电路（“IC”）的方法。 该方法接收具有用于可配置电路的多组操作的设计以在不同的操作周期中执行的设计。 对于至少具有开始操作和结束操作的第一组操作，该方法至少部分地基于特定操作相对于开始的位置而将第一组中的特定操作分配到第一操作周期，以及 结束操作。

    Configurable circuits, IC's, and systems
    5.
    发明授权
    Configurable circuits, IC's, and systems 有权
    可配置电路，IC和系统

    公开(公告)号：US08638119B2

    公开(公告)日：2014-01-28

    申请号：US13476203

    申请日：2012-05-21

    申请人： Herman Schmit ,  Michael Butts ,  Brad L. Hutchings ,  Steven Teig

    发明人： Herman Schmit ,  Michael Butts ,  Brad L. Hutchings ,  Steven Teig

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17752 ,  H03K19/17756 ,  H03K19/17776

    摘要： Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes a logic circuit for receiving input data sets and configuration data sets and performing several functions on the input data sets. Each configuration data set specifies a particular function that the logic circuit has to perform on the input data set. The IC also includes a connection circuit for supplying sets of the configuration data to the logic circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the logic circuit to perform two different functions on the input data.

    摘要翻译： 本发明的一些实施例提供了一种可配置的集成电路（IC）。 IC包括用于接收输入数据集和配置数据集并在输入数据集上执行若干功能的逻辑电路。 每个配置数据集指定逻辑电路必须在输入数据集上执行的特定功能。 IC还包括用于在至少特定时间段以特定速率将配置数据提供给逻辑电路的连接电路。 至少两个提供的配置数据集是不同的，并且配置逻辑电路以在输入数据上执行两个不同的功能。

    Method and system for distributing clock signals on non Manhattan semiconductor integrated circuits
    6.
    发明授权
    Method and system for distributing clock signals on non Manhattan semiconductor integrated circuits 失效
    在非曼哈顿半导体集成电路上分配时钟信号的方法和系统

    公开(公告)号：US08438525B2

    公开(公告)日：2013-05-07

    申请号：US12644001

    申请日：2009-12-21

    申请人： Steven Teig ,  Raghu Chalasani ,  Akira Fujimura

    发明人： Steven Teig ,  Raghu Chalasani ,  Akira Fujimura

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F1/10 ,  G06F2217/62

    摘要： The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network.

    摘要翻译： 本发明介绍了用于在集成电路布局中路由时钟信号的方法，系统和架构。 引入的时钟信号时钟信号结构以非曼哈顿路由呈现。 在第一实施例中，传统的递归H时钟信号结构在变换坐标系之后呈现，从而呈现旋转的递归H时钟信号结构。 在另一个实施例中，使用递归Y结构来创建时钟信号结构。 递归Y结构也可以以旋转的对准来实现。 对于时钟信号冗余，可以使用非曼哈顿布线来创建时钟信号网状网络。

    Configurable integrated circuit with built-in turns
    8.
    发明授权
    Configurable integrated circuit with built-in turns 有权
    具有内置转弯的可组态集成电路

    公开(公告)号：US08415973B2

    公开(公告)日：2013-04-09

    申请号：US13189486

    申请日：2011-07-22

    申请人： Andre Rohe ,  Steven Teig

    发明人： Andre Rohe ,  Steven Teig

    IPC分类号： H03K19/173 ,  G06F17/50

    CPC分类号： H03K19/17736 ,  H03K19/17796

    摘要： Some embodiments of the invention provide an integrated circuit (“IC”) that includes numerous configurable nodes arranged in an array having several rows and columns. In some embodiments, the configurable nodes include a first group of configurable aligned along a particular direction and a second group of configurable nodes aligned along a different direction. The IC also includes a set of direct offset turn connections arranged across the node array in a repetitive nested architecture. Each direct offset turn connection connects a node from the first group of configurable nodes to a node from the second group of configurable nodes. Each direct offset turn connection includes at least two wire segments that are arranged in at least two different directions and intersect to define a turn. No direct offset turn connection overlaps with another direct offset turn connection.

    摘要翻译： 本发明的一些实施例提供了一种集成电路（IC），其包括以具有多个行和列的阵列布置的多个可配置节点。 在一些实施例中，可配置节点包括沿着特定方向可配置对准的第一组和沿着不同方向对准的第二组可配置节点。 IC还包括一组以重复嵌套架构跨越节点阵列布置的直接偏移转接连接。 每个直接偏移转弯连接将节点从第一组可配置节点连接到来自第二组可配置节点的节点。 每个直接偏移转弯连接包括至少两个线段，其布置在至少两个不同的方向上并相交以限定转弯。 没有直接偏移转弯连接与另一个直接偏移转弯连接重叠。