知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

13 条记录 (耗时 0.014 秒)

    Microelectromechanical structure (MEMS) monitoring
    1.
    发明授权
    Microelectromechanical structure (MEMS) monitoring 失效
    微机电结构（MEMS）监控

    公开(公告)号：US08513948B2

    公开(公告)日：2013-08-20

    申请号：US12951515

    申请日：2010-11-22

    申请人： Jonathan P. Ebbers ,  Kenneth J. Goodnow ,  Stephen Gerard Shuma ,  Peter A. Twombly

    发明人： Jonathan P. Ebbers ,  Kenneth J. Goodnow ,  Stephen Gerard Shuma ,  Peter A. Twombly

    IPC分类号： G01R31/327 ,  G01R27/26

    CPC分类号： B81C99/003 ,  B81B2203/0118

    摘要： A MEMS component is monitored to determine its status. Sensors are deployed to sense the MEMS component and produce detection signals that are analyzed to determine the MEMS component state. An indicator device alerts a user of the status, particularly if the MEMS component has failed. Additionally, the MEMS component monitoring system may be practiced as a design structure encoded on computer readable storage media as part of a circuit design system.

    摘要翻译： 监测MEMS组件以确定其状态。 部署传感器以感测MEMS组件并产生被分析以检测MEMS组件状态的检测信号。 指示器设备向用户通知状态，特别是如果MEMS组件出现故障。 另外，作为电路设计系统的一部分，可以将MEMS部件监视系统实施为在计算机可读存储介质上编码的设计结构。

    Repair of memory hard failures during normal operation, using ECC and a hard fail identifier circuit
    2.
    发明授权
    Repair of memory hard failures during normal operation, using ECC and a hard fail identifier circuit 失效
    在正常操作期间修复内存硬故障，使用ECC和硬失败标识符电路

    公开(公告)号：US07386771B2

    公开(公告)日：2008-06-10

    申请号：US11275464

    申请日：2006-01-06

    申请人： Stephen Gerard Shuma

    发明人： Stephen Gerard Shuma

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1008

    摘要： A memory sub-system and a method for operating the same. The memory sub-system includes (a) a main memory, (b) an ECC circuit, (c) a hard fail identifier circuit, (d) a repair circuit, (e) a redundant memory, and (f) a threshold setting circuit. The ECC circuit is capable of (i) detecting a first bit fail, (ii) sending an error flag signal to the hard fail identifier circuit, (iii) sending a first location address, a first bit location of the first bit fail, and a repaired data from the first location address to the hard fail identifier circuit. The hard fail identifier circuit is capable of (i) determining the number of times of failure occurring at the first bit fail, (ii) determining whether the number of times of failure is equal to a predetermined threshold value, and (iii) if so, sending a threshold reached signal.

    摘要翻译： 一种存储器子系统及其操作方法。 存储器子系统包括（a）主存储器，（b）ECC电路，（c）硬故障标识符电路，（d）修复电路，（e）冗余存储器，以及（f）阈值设置 电路。 ECC电路能够（i）检测第一比特失败，（ii）向硬故障标识符电路发送错误标志信号，（iii）发送第一位置地址，第一比特失败的第一比特位置，以及 从第一位置地址到硬故障标识符电路的修复数据。 硬故障识别电路能够（i）确定在第一比特失败时发生的故障次数，（ii）确定故障次数是否等于预定阈值，以及（iii）如果是 发送阈值达到信号。

    Least significant bit and guard bit extractor
    3.
    发明授权
    Least significant bit and guard bit extractor 失效
    最低有效位和保护位提取器

    公开(公告)号：US5841683A

    公开(公告)日：1998-11-24

    申请号：US718272

    申请日：1996-09-20

    申请人： Roland Albert Bechade ,  Robert Hayosh ,  Stephen Gerard Shuma

    发明人： Roland Albert Bechade ,  Robert Hayosh ,  Stephen Gerard Shuma

    IPC分类号： G06F7/57 ,  G06F7/76 ,  G06F5/01

    CPC分类号： G06F7/764 ,  G06F7/483 ,  G06F7/49952

    摘要： In connection with a logic circuit including a mask generator for determining a value for a so-called "sticky bit" in a binary number to be truncated and rounded, an intermediate signal is taken from the mask generator and an Exclusive-OR function applied to adjacent bits to generate a second mask containing or adjacent to a transition between the portion of the number to be dropped and the portion to be retained in the truncated number. The second mask is applied to different overlapping groups of bits in a portion of the number which contains the least significant bit and the guard bit as determined from the number of bits to be dropped, for example, by shifting out from a shifter, as the number is truncated and rounded to extract a specific bit in each group of bits. By extracting such specific bits using a mask, the extraction process is removed from the critical path of the processor which includes the shifter and the extraction process can proceed in parallel with the shifting process.

    摘要翻译： 结合包括掩模发生器的逻辑电路，用于确定要截断和舍入的二进制数中所谓的“粘性位”的值，从掩码发生器获取中间信号，并将异或功能应用于 相邻位以产生包含或相邻待丢弃数量的部分与要保留在截断数中的部分之间的转换的第二掩码。 第二掩码被应用于数字的不同的重叠组，其中包含最低有效位和保护位，例如通过从移位器移出，从被丢弃的位的数量确定，作为 数字被截断并舍入，以提取每组位中的特定位。 通过使用掩码提取这样的特定比特，提取处理从包括移位器的处理器的关键路径中移除，并且提取处理可以与移位处理并行进行。

    Address limit check apparatus with conditional carry logic
    4.
    发明授权
    Address limit check apparatus with conditional carry logic 失效
    具有条件进位逻辑的地址限制检查装置

    公开(公告)号：US5787492A

    公开(公告)日：1998-07-28

    申请号：US629697

    申请日：1996-04-09

    申请人： Stephen Gerard Shuma ,  Robert Francis Hayosh

    发明人： Stephen Gerard Shuma ,  Robert Francis Hayosh

    IPC分类号： G06F7/50 ,  G06F7/507 ,  G06F9/34 ,  G06F12/00

    CPC分类号： G06F7/507 ,  G06F9/34

    摘要： An effective address limit checker reduces the logic delay in the limit checking path. The address limit checker comprises an effective address (EA) adder and limit check logic. The EA adder includes a first carry save adder receiving a displacement, an index and a base address for calculating an effective address, and a second carry select adder receiving partial sum and carry outputs of said first adder for calculating an effective address carry out. The outputs of the EA adder are input to the limit checking logic together with an address limit value and an addressability mode field. The limit checking logic includes a third adder for calculating first partial limit information based on the first adder results and the limit value, and a fourth adder for calculating second partial limit information based on the first adder results and the limit value and conditioned carry out values of the third adder. The third and fourth adders are each composed of a carry save adder and a carry select adder. Conditional carry logic responsive to output values of the third adder controls the operation of the fourth adder based on the addressability mode field. Limit exceeded logic responsive to the carry out of the fourth adder and the second adder asserts a limit check condition.

    摘要翻译： 有效地址限制检查器可以减少极限检查路径中的逻辑延迟。 地址限制检查器包括有效地址（EA）加法器和限制检查逻辑。 EA加法器包括接收位移的第一进位保存加法器，用于计算有效地址的索引和基址，以及接收部分和的第二进位选择加法器，并且传送用于计算有效地址执行的所述第一加法器的输出。 EA加法器的输出与地址极限值和可寻址模式字段一起输入到限制检查逻辑。 极限检查逻辑包括第三加法器，用于基于第一加法器结果和极限值来计算第一部分限制信息;以及第四加法器，用于基于第一加法器结果和限制值和条件执行值计算第二部分限制信息 的第三加法器。 第三和第四加法器由进位保存加法器和进位选择加法器组成。 响应于第三加法器的输出值的条件进位逻辑基于可寻址模式字段来控制第四加法器的操作。 响应于第四加法器的进位，限制超过逻辑，第二加法器确定极限检查条件。

    METHODS AND CIRCUITS TO REDUCE THRESHOLD VOLTAGE TOLERANCE AND SKEW IN MULTI-THRESHOLD VOLTAGE APPLICATIONS
    5.
    发明申请
    METHODS AND CIRCUITS TO REDUCE THRESHOLD VOLTAGE TOLERANCE AND SKEW IN MULTI-THRESHOLD VOLTAGE APPLICATIONS 审中-公开
    降低多电压电压应用中阈值电压公差和电流的方法和电路

    公开(公告)号：US20080246533A1

    公开(公告)日：2008-10-09

    申请号：US12138514

    申请日：2008-06-13

    申请人： Corey Kenneth Barrows ,  Douglas W. Kemerer ,  Stephen Gerard Shuma ,  Douglas Willard Stout ,  Oscar Conrad Strohacker ,  Mark Steven Styduhar ,  Paul Steven Zuchowski

    发明人： Corey Kenneth Barrows ,  Douglas W. Kemerer ,  Stephen Gerard Shuma ,  Douglas Willard Stout ,  Oscar Conrad Strohacker ,  Mark Steven Styduhar ,  Paul Steven Zuchowski

    IPC分类号： H03K3/01

    CPC分类号： G06F17/5063 ,  H01L27/088 ,  H01L27/092

    摘要： A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit configured to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator configured to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.

    摘要翻译： 一种用于调整集成电路性能的电路和方法，所述电路包括：具有相应的第一和第二阈值电压的第一和第二组FET，所述第一阈值电压不同于所述第二阈值电压; 包含第一组FET的至少一个FET的第一监视器电路和包含第二组FET的至少一个FET的第二监视电路; 比较电路，被配置为基于所述第一监视电路的性能测量和所述第二监视电路的性能测量来产生比较信号; 以及控制单元，被配置为基于所述比较信号向电压调节器产生控制信号，所述电压调节器被配置为向所述第二组FET的FET的阱提供偏置电压，所述偏置电压的值基于所述控制 信号。

    Circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications
    6.
    发明授权
    Circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications 有权
    降低多阈值电压应用中阈值电压容限和偏斜的电路

    公开(公告)号：US07459958B2

    公开(公告)日：2008-12-02

    申请号：US11424961

    申请日：2006-06-19

    申请人： Corey Kenneth Barrows ,  Douglas W. Kemerer ,  Stephen Gerard Shuma ,  Douglas Willard Stout ,  Oscar Conrad Strohacker ,  Mark Steven Styduhar ,  Paul Steven Zuchowski

    发明人： Corey Kenneth Barrows ,  Douglas W. Kemerer ,  Stephen Gerard Shuma ,  Douglas Willard Stout ,  Oscar Conrad Strohacker ,  Mark Steven Styduhar ,  Paul Steven Zuchowski

    IPC分类号： H03K3/01

    CPC分类号： G06F17/5063 ,  H01L27/088 ,  H01L27/092

    摘要： A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit adapted to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit adapted to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator adapted to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.

    摘要翻译： 一种用于调整集成电路性能的电路和方法，所述电路包括：具有相应的第一和第二阈值电压的第一和第二组FET，所述第一阈值电压不同于所述第二阈值电压; 包含第一组FET的至少一个FET的第一监视器电路和包含第二组FET的至少一个FET的第二监视电路; 比较电路，其适于基于第一监视电路的性能测量和第二监视电路的性能测量来产生比较信号; 以及控制单元，其适于基于所述比较信号向所述电压调节器产生控制信号，所述电压调节器适于向所述第二组FET的FET的阱提供偏置电压，所述偏置电压的值基于所述控制 信号。

    REPAIR OF MEMORY HARD FAILURES DURING NORMAL OPERATION, USING ECC AND A HARD FAIL IDENTIFIER CIRCUIT
    9.
    发明申请
    REPAIR OF MEMORY HARD FAILURES DURING NORMAL OPERATION, USING ECC AND A HARD FAIL IDENTIFIER CIRCUIT 失效
    在正常操作期间修复存储器硬件故障，使用ECC和硬件故障标识符电路

    公开(公告)号：US20080195888A1

    公开(公告)日：2008-08-14

    申请号：US12105338

    申请日：2008-04-18

    申请人： Stephen Gerard Shuma

    发明人： Stephen Gerard Shuma

    IPC分类号： G06F11/20 ,  G06F11/07

    CPC分类号： G06F11/1008

    摘要： A memory sub-system and a method for operating the same. The memory sub-system includes (a) a main memory, (b) an ECC circuit, (c) a hard fail identifier circuit, (d) a repair circuit, (e) a redundant memory, and (f) a threshold setting circuit. The ECC circuit is capable of (i) detecting a first bit fail, (ii) sending an error flag signal to the hard fail identifier circuit, (iii) sending a first location address, a first bit location of the first bit fail, and a repaired data from the first location address to the hard fail identifier circuit. The hard fail identifier circuit is capable of (i) determining the number of times of failure occurring at the first bit fail, (ii) determining whether the number of times of failure is equal to a predetermined threshold value, and (iii) if so, sending a threshold reached signal.

    摘要翻译： 一种存储器子系统及其操作方法。 存储器子系统包括（a）主存储器，（b）ECC电路，（c）硬故障标识符电路，（d）修复电路，（e）冗余存储器，以及（f）阈值设置 电路。 ECC电路能够（i）检测第一比特失败，（ii）向硬故障标识符电路发送错误标志信号，（iii）发送第一位置地址，第一比特失败的第一比特位置，以及 从第一位置地址到硬故障标识符电路的修复数据。 硬故障识别电路能够（i）确定在第一比特失败时发生的故障次数，（ii）确定故障次数是否等于预定阈值，以及（iii）如果是 发送阈值达到信号。