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公开(公告)号：US20120131389A1
公开(公告)日：2012-05-24
申请号：US13299578
申请日：2011-11-18
CPC分类号： G06F11/004 , G06F11/143 , G06F11/1438 , G06F11/1482
摘要： Methods and systems for cross-layer forgiveness exploitation include executing one or more applications using a processing platform that includes a first reliable processing core and at least one additional processing core having a lower reliability than the first processing core, modifying application execution according to one or more best-effort techniques to improve performance, and controlling parameters associated with the processing platform and the best-effort layer that control performance and error rate such that performance is maximized in a region of low hardware-software interference.
摘要翻译： 用于跨层宽恕开发的方法和系统包括使用包括第一可靠处理核心和至少一个具有比第一处理核心更低可靠性的附加处理核心的处理平台执行一个或多个应用程序，根据一个或多个 更精心的技术来提高性能，以及控制与处理平台相关的参数和尽力而为的层，以控制性能和错误率，使得在低硬件 - 软件干扰的区域中性能最大化。
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公开(公告)号：US08762794B2
公开(公告)日：2014-06-24
申请号：US13299578
申请日：2011-11-18
IPC分类号： G06F11/00
CPC分类号： G06F11/004 , G06F11/143 , G06F11/1438 , G06F11/1482
摘要： Methods and systems for cross-layer forgiveness exploitation include executing one or more applications using a processing platform that includes a first reliable processing core and at least one additional processing core having a lower reliability than the first processing core, modifying application execution according to one or more best-effort techniques to improve performance, and controlling parameters associated with the processing platform and the best-effort layer that control performance and error rate such that performance is maximized in a region of low hardware-software interference.
摘要翻译： 用于跨层宽恕开发的方法和系统包括使用包括第一可靠处理核心和至少一个具有比第一处理核心更低可靠性的附加处理核心的处理平台执行一个或多个应用程序，根据一个或多个 更精心的技术来提高性能，以及控制与处理平台相关的参数和尽力而为的层，以控制性能和错误率，使得在低硬件 - 软件干扰的区域中性能最大化。
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3.发明申请公开(公告)号：US20100088492A1
公开(公告)日：2010-04-08
申请号：US12399195
申请日：2009-03-06
IPC分类号： G06F9/30
CPC分类号： G06F9/545 , G06F8/00 , G06F9/4887 , G06F2209/485 , G06F2209/542
摘要： Implementations of the present principles include Best-effort computing systems and methods. In accordance with various exemplary aspects of the present principles, a application computation requests directed to a processing platform may be intercepted and classified as either guaranteed computations or best-effort computations. Best-effort computations may be dropped to improve processing performance while minimally affecting the end result of application computations. In addition, interdependencies between best-effort computations may be relaxed to improve parallelism and processing speed while maintaining accuracy of computation results.
摘要翻译： 本原则的实施包括尽力而为的计算系统和方法。 根据本原理的各种示例性方面，针对处理平台的应用计算请求可被截取并分类为保证计算或尽力而为计算。 可以降低最大的努力以提高处理性能，同时最小程度上影响应用程序计算的最终结果。 此外，可以放宽努力计算之间的相互依赖性，以提高并行性和处理速度，同时保持计算结果的准确性。
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4.发明授权Systems and methods for implementing best-effort parallel computing frameworks 有权实现尽力而为并行计算框架的系统和方法公开(公告)号：US08286172B2
公开(公告)日：2012-10-09
申请号：US12399195
申请日：2009-03-06
IPC分类号： G06F9/46
CPC分类号： G06F9/545 , G06F8/00 , G06F9/4887 , G06F2209/485 , G06F2209/542
摘要： Implementations of the present principles include Best-effort computing systems and methods. In accordance with various exemplary aspects of the present principles, a application computation requests directed to a processing platform may be intercepted and classified as either guaranteed computations or best-effort computations. Best-effort computations may be dropped to improve processing performance while minimally affecting the end result of application computations. In addition, interdependencies between best-effort computations may be relaxed to improve parallelism and processing speed while maintaining accuracy of computation results.
摘要翻译： 本原则的实施包括尽力而为的计算系统和方法。 根据本原理的各种示例性方面，针对处理平台的应用计算请求可被截取并分类为保证计算或尽力而为计算。 可以降低最大的努力以提高处理性能，同时最小程度上影响应用程序计算的最终结果。 此外，可以放宽努力计算之间的相互依赖性，以提高并行性和处理速度，同时保持计算结果的准确性。
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公开(公告)号：US20120084747A1
公开(公告)日：2012-04-05
申请号：US13235988
申请日：2011-09-19
IPC分类号： G06F9/44
CPC分类号： G06F17/10 , G06F9/5066 , G06K9/6223
摘要： Methods and systems for iterative convergence include performing at least one global iteration. Each global iteration includes partitioning input data into multiple input data partitions according to an input data partitioning function, partitioning a model into multiple model partitions according to a model partitioning function, performing at least one local iteration using a processor to compute sub-problems formed from a model partition and an input data partition to produce multiple locally updated models, and combining the locally updated models from the at least one local iteration according to a model merging function to produce a merged model.
摘要翻译： 用于迭代收敛的方法和系统包括执行至少一个全局迭代。 每个全局迭代包括根据输入数据分区功能将输入数据分割成多个输入数据分区，根据模型划分功能将模型划分为多个模型分区，使用处理器执行至少一个局部迭代，以计算从 模型分区和输入数据分区，以产生多个本地更新的模型，以及根据模型合并功能组合来自至少一个局部迭代的本地更新的模型以产生合并的模型。
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公开(公告)号：US20050097413A1
公开(公告)日：2005-05-05
申请号：US10795231
申请日：2004-03-09
IPC分类号： G01R31/28 , H01L20060101
CPC分类号： G06F11/263 , G01R31/318547
摘要： An integrated circuit comprising at least one system level decompressor and at least a first hardware block associated with a core level decompressor. The system level decompressor is capable of performing system level decompression of received compressed test data to form partially decompressed test data. The core level decompressor being capable of performing core level decompression of the partially decompressed test data.
摘要翻译： 一种集成电路，包括至少一个系统级解压缩器和至少与核心级解压缩器相关联的第一硬件块。 系统级解压缩器能够对接收到的压缩测试数据执行系统级解压缩，形成部分解压缩的测试数据。 核心级解压缩器能够执行部分解压缩测试数据的核心级解压缩。
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公开(公告)号：US07278123B2
公开(公告)日：2007-10-02
申请号：US10795231
申请日：2004-03-09
IPC分类号： G06F17/50
CPC分类号： G06F11/263 , G01R31/318547
摘要： An integrated circuit comprising at least one system level decompressor and at least a first hardware block associated with a core level decompressor. The system level decompressor is capable of performing system level decompression of received compressed test data to form partially decompressed test data. The core level decompressor being capable of performing core level decompression of the partially decompressed test data.
摘要翻译： 一种集成电路，包括至少一个系统级解压缩器和至少与核心级解压缩器相关联的第一硬件块。 系统级解压缩器能够对接收到的压缩测试数据执行系统级解压缩，形成部分解压缩的测试数据。 核心级解压缩器能够执行部分解压缩测试数据的核心级解压缩。
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8.发明申请Apparatus and Method for Improving Security of a Bus Based System Through Communication Architecture Enhancements 审中-公开通过通信架构增强功能提高总线系统安全性的装置和方法公开(公告)号：US20070101424A1
公开(公告)日：2007-05-03
申请号：US11458834
申请日：2006-07-20
IPC分类号： H04L9/00 , G06F12/14 , G06F11/00 , H04L9/32 , G06F17/00 , G06F11/30 , H04K1/00 , G06F12/16 , G06F15/18 , G08B23/00
CPC分类号： G06F21/85 , G06F13/4031
摘要： A security policy associated with a system is evaluated. The system includes a communication bus having a data bus and a plurality of components interconnected via the communication bus. The system also includes a circuit configured to evaluate a security policy associated with the system by reading at least one data bus signal associated with a transaction between at least two of the plurality of components.
摘要翻译： 评估与系统相关联的安全策略。 该系统包括具有数据总线和经由通信总线互连的多个部件的通信总线。 该系统还包括被配置为通过读取与多个组件中的至少两个之间的事务相关联的至少一个数据总线信号来评估与系统相关联的安全策略的电路。
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公开(公告)号：US20060080076A1
公开(公告)日：2006-04-13
申请号：US11200393
申请日：2005-08-09
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A power estimation framework based on a network of power monitors that observe component- and system-level execution and power statistics at run time. Based on those statistics, the power monitors (i) select between multiple alternative power models for each component and/or (ii) configure the component power models to best negotiate the trade-off between efficiency and accuracy. This approach effectuates a co-coordinated, adaptive, spatio-temporal allocation of computational effort for power estimation. This approach yields large reductions in power estimation overhead while minimally impacting power estimation accuracy.
摘要翻译： 基于功率监视器网络的功率估计框架，其在运行时观察组件和系统级执行和功率统计。 基于这些统计，功率监视器（i）为每个组件选择多个替代功率模型，和/或（ii）配置组件功率模型以最佳地协商效率和精度之间的折衷。 这种方法实现了功率估计的计算工作的共同协调的，适应性的时空分配。 这种方法在最小程度上影响功率估计精度的同时，功率估计开销大幅降低。
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公开(公告)号：US20050204155A1
公开(公告)日：2005-09-15
申请号：US10795385
申请日：2004-03-09
IPC分类号： H04L9/00
CPC分类号： G06F21/575 , G06F21/71 , G06F21/79 , G06F21/85
摘要： A system comprising at least one host processor, at least one security processor and a first memory that is exclusively accessible only by the security processor.
摘要翻译： 一种包括至少一个主处理器，至少一个安全处理器和仅由安全处理器唯一访问的第一存储器的系统。
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