公开(公告)号：US6061311A

公开(公告)日：2000-05-09

申请号：US991878

申请日：1997-12-16

申请人： Shigetaka Asano ,  Masaru Sawada

发明人： Shigetaka Asano ,  Masaru Sawada

IPC分类号： G06F3/06 ,  G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  G11B27/30 ,  G11B5/09

CPC分类号： G11B20/1833 ,  G11B20/1217 ,  G11B27/3027 ,  G11B2220/2562

摘要： A device for reproducing data recorded on a recording medium, such as a magnetic disk or an optical disk, includes a data reading apparatus and a data reproducing apparatus. The data reading apparatus reads sector data from the reading medium, including data, synch-byte signals and control signals, and generates a clock signal. The data reading apparatus reproduces the recorded data in accordance with the clock signal. When a synch-byte signal is detected by the reading apparatus, transmission of control signals to the reproducing apparatus is inhibited. In addition, lost data is recovered using other data and an ECC code.

摘要翻译： 用于再现记录在诸如磁盘或光盘的记录介质上的数据的装置包括数据读取装置和数据再现装置。 数据读取装置从读取介质读取包括数据，同步字节信号和控制信号的扇区数据，并产生时钟信号。 数据读取装置根据时钟信号再现记录的数据。 当读取装置检测到同步字节信号时，禁止向再现装置发送控制信号。 此外，使用其他数据和ECC代码恢复丢失的数据。

公开(公告)号：US07098818B1

公开(公告)日：2006-08-29

申请号：US11166978

申请日：2005-06-24

申请人： Masaru Sawada ,  Toshio Ito ,  Toshihiko Morita

发明人： Masaru Sawada ,  Toshio Ito ,  Toshihiko Morita

IPC分类号： H03M5/00 ,  G06F15/00 ,  G06F11/00

CPC分类号： H03M5/145

摘要： When a zero run, which violating G constraint of a run-length-limited (RLL) code, is detected from the data stored in a first input register 1111 and a second input register 1112, bits before and after the zero run is transferred to a temporary register 1150 via a bus for zero run removal 1130 to be combined to each other. Thus, by effectively using the mechanism of bus transfer, a circuit can be simplified, thereby realizing a small circuit.

摘要翻译： 当从存储在第一输入寄存器1111和第二输入寄存器1112中的数据检测违反游程长度限制（RLL）代码的G约束的零运行时，将零运行之前和之后的位传送到 一个临时寄存器1150通过总线进行零运行移除1130以彼此组合。 因此，通过有效地利用总线传输的机制，可以简化电路，从而实现小电路。

公开(公告)号：US06600779B1

公开(公告)日：2003-07-29

申请号：US09274350

申请日：1999-03-23

申请人： Masaru Sawada ,  Tsuyoshi Tomita ,  Yoshitaka Nakata ,  Tsunehiko Moriuchi ,  Kenichi Yamakura ,  Hideaki Tanishima ,  Fumiaki Uematsu ,  Koji Horibe ,  Manabu Nakano

发明人： Masaru Sawada ,  Tsuyoshi Tomita ,  Yoshitaka Nakata ,  Tsunehiko Moriuchi ,  Kenichi Yamakura ,  Hideaki Tanishima ,  Fumiaki Uematsu ,  Koji Horibe ,  Manabu Nakano

IPC分类号： H03H730

CPC分类号： G11B20/10009 ,  G11B20/10046 ,  G11B20/18

摘要： A signal processor used to process an analog read signal representing data stored on a magnetic disk allows for a faster read operation without requiring an increase in its circuit area or buffer memory space. The signal processor includes a decision feedback equalizer which selectively provides a feedback signal added to a read signal in reproducing data read from a storage medium. The signal processor also performs error correction. In performing error correction, the load of the error correcting process is detected and the processing speed is altered depending upon the detected load.

摘要翻译： 用于处理表示存储在磁盘上的数据的模拟读取信号的信号处理器允许更快的读取操作，而不需要增加其电路面积或缓冲存储器空间。 信号处理器包括判决反馈均衡器，其在再现从存储介质读取的数据时选择性地提供添加到读取信号的反馈信号。 信号处理器还执行纠错。 在执行纠错时，检测出纠错处理的负载，并且根据检测到的负载改变处理速度。

公开(公告)号：US5848046A

公开(公告)日：1998-12-08

申请号：US869742

申请日：1997-06-05

申请人： Masaru Sawada

发明人： Masaru Sawada

IPC分类号： G06F3/06 ,  G11B20/10 ,  G11B27/30 ,  G11B7/00

CPC分类号： G11B27/3027 ,  G11B20/10

摘要： A signal processing circuit converts a serial analog signal, obtained by sequentially reading data recorded on a disk by a head, to a parallel digital signal to be output. The signal processing circuit also converts an externally input parallel digital signal to a serial analog signal at the time of recording data on the disk and sends the analog signal to the head. The signal processing circuit comprises a converter that converts the serial analog signal of data read from the disk to a serial digital signal and converts the parallel digital signal of externally input data to an analog signal in order to send the analog signal to the head. A shift register converts the serial digital signal received from the converter to a parallel digital signal in a data read mode and converts the parallel digital signal externally input to a serial digital signal to send the serial digital signal to the converter in a data write mode. A processor operates faster than the disk access speed to perform a predetermined reading process on the parallel digital signal received from the shift register to send out the resultant signal and to perform a predetermined writing process on the parallel digital signal externally input to send the resultant signal to the shift register. A program memory, connected to the processor, stores programs associated with the reading process and writing process that are performed by the processor.

摘要翻译： 信号处理电路将通过将由盘头记录在盘上的数据顺序读取得到的串行模拟信号转换成要被输出的并行数字信号。 信号处理电路在将数据记录在盘上时将外部输入的并行数字信号转换为串行模拟信号，并将模拟信号发送到磁头。 信号处理电路包括转换器，其将从盘读取的数据的串行模拟信号转换为串行数字信号，并将外部输入数据的并行数字信号转换为模拟信号，以将模拟信号发送到头部。 移位寄存器将从转换器接收的串行数字信号以数据读取模式转换为并行数字信号，并将外部输入的并行数字信号转换为串行数字信号，以数据写入模式将串行数字信号发送到转换器。 处理器比磁盘访问速度更快地执行对从移位寄存器接收的并行数字信号执行预定的读取处理，以发出结果信号并且对外部输入的并行数字信号执行预定的写入处理以发送结果信号 到移位寄存器。 连接到处理器的程序存储器存储与由处理器执行的读取处理和写入处理相关联的程序。

公开(公告)号：US20060220926A1

公开(公告)日：2006-10-05

申请号：US11201895

申请日：2005-08-11

申请人： Toshio Ito ,  Masaru Sawada ,  Toshihiko Morita

发明人： Toshio Ito ,  Masaru Sawada ,  Toshihiko Morita

IPC分类号： H03M7/00

CPC分类号： G11B20/10009 ,  G11B20/10194 ,  G11B20/1426 ,  G11B2020/1457

摘要： An encoder includes an encoded-bit-string generating unit that generates a plurality of bit strings encoded by scrambling with respect to an input bit string; a DC-component evaluating unit that selects a bit string having a predetermined width in the bit strings generated by the encoded-bit-string generating unit, while shifting bits one by one or every m-bits, where m is a positive integer, and evaluates the DC component in each of the bit strings selected; and a bit-string extracting unit that extracts a bit string with suppressed DC component from among the bit strings encoded, based on a result of an evaluation by the direct-current-component evaluating unit.

摘要翻译： 编码器包括编码比特串生成单元，其生成通过相对于输入比特串的加扰编码的多个比特串; DC分量评估单元，在由位编码比特串生成单元生成的比特串中选择具有预定宽度的比特串，同时移位比特一个或每个m比特，其中m是正整数，以及 评估所选择的每个位串中的直流分量; 以及位串提取单元，其基于直流分量评估单元的评估结果，从编码的比特串中提取具有抑制的DC分量的比特串。

公开(公告)号：US07054088B2

公开(公告)日：2006-05-30

申请号：US10273485

申请日：2002-10-18

申请人： Akihiro Yamazaki ,  Takao Sugawara ,  Motomu Takatsu ,  Masaru Sawada

发明人： Akihiro Yamazaki ,  Takao Sugawara ,  Motomu Takatsu ,  Masaru Sawada

IPC分类号： G11B5/35

CPC分类号： G11B20/10009 ,  G11B5/09 ,  G11B20/18

摘要： A timing recovery unit detects a phase offset and a frequency offset from a head area of reproduction data and initially corrects them. The timing recovery unit stores data in which a head reproduction signal has been made to be discrete by a fixed clock into a buffer. A phase offset detector detects the phase offset from the data head area in parallel with the operation for writing the data into the buffer. At the same time, a frequency offset detector detects the frequency offset from the data head area in parallel with the operation for writing the data into the buffer. A correction value of the detected phase offset and a correction value of the detected frequency offset are initially set into a digital PLL. While the data is read out from the buffer, a frequency lead-in and a phase lead-in are executed in the head area.

公开(公告)号：US07023946B2

公开(公告)日：2006-04-04

申请号：US10288286

申请日：2002-11-06

申请人： Masaru Sawada ,  Tsuyoshi Tomita ,  Yoshitaka Nakata ,  Tsunehiko Moriuchi ,  Kenichi Yamakura ,  Hideaki Tanishima ,  Fumiaki Uematsu ,  Koji Horibe ,  Manabu Nakano

发明人： Masaru Sawada ,  Tsuyoshi Tomita ,  Yoshitaka Nakata ,  Tsunehiko Moriuchi ,  Kenichi Yamakura ,  Hideaki Tanishima ,  Fumiaki Uematsu ,  Koji Horibe ,  Manabu Nakano

IPC分类号： H03D3/24

CPC分类号： G11B20/10009 ,  G11B20/10046 ,  G11B20/18

摘要： A signal processor used to process an analog read signal representing data stored on a magnetic disk allows for a faster read operation without requiring an increase in its circuit area or buffer memory space. The signal processor includes a decision feedback equalizer which selectively provides a feedback signal added to a read signal in reproducing data read from a storage medium. The signal processor also performs error correction. In performing error correction, the load of the error correcting process is detected and the processing speed is altered depending upon the detected load.

公开(公告)号：US06288665B1

公开(公告)日：2001-09-11

申请号：US09568243

申请日：2000-05-09

申请人： Sanroku Tsukamoto ,  Ian Dedic ,  Kuniyoshi Kamei ,  Toshiaki Endo ,  Masaru Sawada ,  Hiroko Murakami

发明人： Sanroku Tsukamoto ,  Ian Dedic ,  Kuniyoshi Kamei ,  Toshiaki Endo ,  Masaru Sawada ,  Hiroko Murakami

IPC分类号： H03M112

CPC分类号： H03M7/165 ,  H03M1/365

摘要： An encoder for an A/D converter includes a plurality of ROM cells connected between bit lines and word lines. Each of the ROM cells is responsive to a word line select signal supplied to a word line associated with each of the ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of the ROM cells. A logic processor is coupled to one of the bit lines and to two of the word lines used to select a ROM cell connected to the bit line. The logic processor produces an output signal indicative of a selection of the ROM cell connected to the bit line, based on word line select signals supplied on the two word lines.

摘要翻译： 用于A / D转换器的编码器包括连接在位线和字线之间的多个ROM单元。 每个ROM单元响应于提供给与每个ROM单元相关联的字线的字线选择信号，用于根据字线选择信号将数字输出信号提供给与每个ROM单元相关联的位线。 逻辑处理器耦合到位线之一和用于选择连接到位线的ROM单元的两条字线。 逻辑处理器基于在两条字线上提供的字线选择信号，产生指示连接到位线的ROM单元的选择的输出信号。

公开(公告)号：US6046694A

公开(公告)日：2000-04-04

申请号：US603607

申请日：1996-02-21

申请人： Sanroku Tsukamoto ,  Ian Dedic ,  Kuniyoshi Kamei ,  Toshiaki Endo ,  Masaru Sawada ,  Hiroko Murakami

发明人： Sanroku Tsukamoto ,  Ian Dedic ,  Kuniyoshi Kamei ,  Toshiaki Endo ,  Masaru Sawada ,  Hiroko Murakami

IPC分类号： H03M1/36 ,  H03M7/16

CPC分类号： H03M7/165 ,  H03M1/365

摘要： An encoder for an A/D converter includes a plurality of ROM cells connected between bit lines and word lines. Each of the ROM cells is responsive to a word line select signal supplied to a word line associated with each of the ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of the ROM cells. A logic processor is coupled to one of the bit lines and to two of the word lines used to select a ROM cell connected to the bit line. The logic processor produces an output signal indicative of a selection of the ROM cell connected to the bit line, based on word line select signals supplied on the two word lines.

摘要翻译： 用于A / D转换器的编码器包括连接在位线和字线之间的多个ROM单元。 每个ROM单元响应于提供给与每个ROM单元相关联的字线的字线选择信号，用于根据字线选择信号将数字输出信号提供给与每个ROM单元相关联的位线。 逻辑处理器耦合到位线之一和用于选择连接到位线的ROM单元的两条字线。 逻辑处理器基于在两条字线上提供的字线选择信号，产生指示连接到位线的ROM单元的选择的输出信号。

公开(公告)号：US5424969A

公开(公告)日：1995-06-13

申请号：US13798

申请日：1993-02-05

申请人： Kenji Yamada ,  Kiichiro Iga ,  Masaru Sawada

发明人： Kenji Yamada ,  Kiichiro Iga ,  Masaru Sawada

IPC分类号： G06F7/544 ,  G06F7/00

CPC分类号： G06F7/5443 ,  G06F2207/3884

摘要： A product-sum operation unit including a multiplying unit, a pipeline register for loading a multiplication result, an adder unit for adding a summand and either an output of the pipeline register or an addend. A timing signal generating unit generates first and second timing signals (T1, T2) that are synchronized with first and second clocks (CK1, CK2). A first instruction latch loads an instruction synchronously with the first timing signal (T1) to output a first control signal. A second instruction latch loads an instruction loaded in the first instruction latch synchronously with the second timing signal (T2) to output the second control signal. A control signal selector outputs the second control signal in response to the first timing signal (T1), and also outputs the first control signal to the adder unit, in response to the second timing signal (T2).

摘要翻译： 产品和运算单元，包括乘法单元，用于加载相乘结果的流水线寄存器，用于加法加法器的加法器单元和流水线寄存器的输出或加数。 定时信号产生单元产生与第一和第二时钟（CK1，CK2）同步的第一和第二定时信号（T1，T2）。 第一指令锁存器与第一定时信号（T1）同步地加载指令以输出第一控制信号。 第二指令锁存器与第二定时信号（T2）同步地加载与第一指令锁存器相加的指令，以输出第二控制信号。 控制信号选择器响应于第一定时信号（T1）输出第二控制信号，并且还响应于第二定时信号（T2）将第一控制信号输出到加法器单元。