公开(公告)号：US20090147902A1

公开(公告)日：2009-06-11

申请号：US12170742

申请日：2008-07-10

申请人： Shen-Iuan LIU ,  You-Jen WANG

发明人： Shen-Iuan LIU ,  You-Jen WANG

IPC分类号： H03D3/24

CPC分类号： H03L7/10 ,  H03L7/091 ,  H03L7/093 ,  H03L7/0991 ,  H03L2207/06 ,  H03L2207/50

摘要： An all-digital phase-locked loop (ADPLL) composed of digital circuits is provided. The ADPLL includes a phase-frequency detector (PFD), a control unit, a digital controlled oscillator (DCO), and a plurality of frequency dividers. A first frequency divider divides a frequency of a feedback signal CKOUT by a natural number M to generate a first output signal CKOUT/M. The PFD generates a decrement signal dn and an increment signal up, based on a phase difference and a frequency between a first reference clock signal CKIN and the first output signal CKOUT/M. The DCO generates a clock signal CKDCO based on the digital control signals. A second frequency divider receives the digital control signals from the control unit and the CKDCO from the DCO and divides the frequency of the CKDCO by a bit number of the digital control signals to generate a feedback signal CKOUT to the first frequency divider.

摘要翻译： 提供由数字电路组成的全数字锁相环（ADPLL）。 ADPLL包括相位频率检测器（PFD），控制单元，数字控制振荡器（DCO）和多个分频器。 第一分频器将反馈信号CKOUT的频率除以自然数M以产生第一输出信号CKOUT / M。 PFD基于第一参考时钟信号CKIN和第一输出信号CKOUT / M之间的相位差和频率产生递增信号dn和递增信号up。 DCO基于数字控制信号产生时钟信号CKDCO。 第二分频器从DCO接收来自控制单元和CKDCO的数字控制信号，并将CKDCO的频率除以数字控制信号的位数，以产生到第一分频器的反馈信号CKOUT。

公开(公告)号：US20120056769A1

公开(公告)日：2012-03-08

申请号：US12874462

申请日：2010-09-02

申请人： You-Jen WANG ,  Shen-Iuan LIU ,  Feng Wei KUO ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

发明人： You-Jen WANG ,  Shen-Iuan LIU ,  Feng Wei KUO ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

IPC分类号： H03M1/50

CPC分类号： G04F10/005

摘要： Methods and apparatuses for time to digital conversion (TDC) are disclosed. A timing circuit comprises a TDC circuit, a calibration module, and a correction module. The TDC circuit is configured to provide a timing signal indicative of a timing difference between edges of a periodic reference clock signal and a variable feedback signal. The TDC circuit is also configured to provide a delay signal that is variably delayed relative to the reference clock signal. The calibration module is configured to provide a calibration signal to increase and decrease a total delay of the TDC circuit based on a time delay of the calibration signal plus a time delay of a correction signal. The correction module, which is configured to receive the timing signal and provide the correction signal, minimizes harmonic spurs in a frequency response of the timing signal by operating at a frequency of the reference clock signal.

摘要翻译： 公开了时间到数字转换（TDC）的方法和装置。 定时电路包括TDC电路，校准模块和校正模块。 TDC电路被配置为提供指示周期性参考时钟信号的边沿与可变反馈信号之间的定时差的定时信号。 TDC电路还被配置为提供相对于参考时钟信号可变地延迟的延迟信号。 校准模块被配置为提供校准信号，以根据校准信号的时间延迟加上校正信号的时间延迟来增加和减少TDC电路的总延迟。 被配置为接收定时信号并提供校正信号的校正模块通过在参考时钟信号的频率下工作来最小化定时信号的频率响应中的谐波杂散。

公开(公告)号：US20110304372A1

公开(公告)日：2011-12-15

申请号：US12813620

申请日：2010-06-11

申请人： You-Jen WANG ,  Shen-Iuan LIU ,  Feng Wei KUO ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

发明人： You-Jen WANG ,  Shen-Iuan LIU ,  Feng Wei KUO ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

IPC分类号： H03H11/26

CPC分类号： G04F10/005

摘要： A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high.

摘要翻译： 时间放大器电路具有第一和第二反相器以及第一和第二下拉通路。 每个反相器包括第一NMOS晶体管和第一PMOS晶体管。 第一NMOS晶体管的源极直接或通过具有耦合到相应输入节点的栅极的第一附加NMOS晶体管耦合到接地节点。 第一和第二反相器分别耦合到第一和第二输入节点以及第一和第二输出节点。 第一下拉路径从第一输出节点到接地节点，并且响应于第一输入信号而使第二输出信号为高。 第二下拉路径从第二输出节点到地，并且响应于第二输入信号并且第一输出信号为高而使能。