公开(公告)号：US20200073155A1

公开(公告)日：2020-03-05

申请号：US16535313

申请日：2019-08-08

申请人： Sharp Kabushiki Kaisha

发明人： Hideki KITAGAWA ,  Yoshihito HARA ,  Masaki MAEDA ,  Tatsuya KAWASAKI ,  Yoshiharu HIRATA ,  Hajime IMAI ,  Tohru DAITOH

IPC分类号： G02F1/03 ,  G02F1/1362 ,  H01L27/12

摘要： An electronic component board includes a conductive film, an insulating film, and a transparent electrode film. The insulating film is disposed in a layer upper than the conductive film to cover a side surface and an upper surface of the conductive film. The transparent electrode film is disposed in a layer upper than the insulating film. The transparent electrode film includes an electrode portion and a covering portion. The electrode portion includes an electrode. The electrode portion is electrically connected to the conductive film. The covering portion is separated from the electrode portion and electrically insulated from the conductive film and the electrode portion to overlap the conductive film and the insulating film that covers the conductive film.

公开(公告)号：US20190102025A1

公开(公告)日：2019-04-04

申请号：US16145426

申请日：2018-09-28

申请人： Sharp Kabushiki Kaisha

发明人： Hideki KITAGAWA ,  Tohru DAITOH ,  Hajime IMAI ,  Yoshihito HARA ,  Masaki MAEDA ,  Toshikatsu ITOH ,  Tatsuya KAWASAKI

IPC分类号： G06F3/041 ,  G06F3/044 ,  G09G3/36

摘要： A display panel includes a substrate, pixel electrodes, position detection electrodes, switching components, position detection lines, and an insulating film. The pixel electrodes are disposed on the substrate. The position detection electrodes are disposed on the substrate and configured to detect positions of input by a position input member. The switching components are disposed in a layer lower than layers in which the pixel electrodes and the position detection electrodes are disposed on the substrate and connected to the pixel electrodes, respectively. The position detection lines are disposed in a layer lower than the layer in which the switching components are disposed and electrically connected to the position detection electrodes. The insulating film is disposed between the position detection lines and the switching components.

公开(公告)号：US20190081077A1

公开(公告)日：2019-03-14

申请号：US16084568

申请日：2017-03-13

申请人： Sharp Kabushiki Kaisha

发明人： Masahiko SUZUKI ,  Tetsuo KIKUCHI ,  Hajime IMAI ,  Hisao OCHI ,  Hideki KITAGAWA ,  Setsuji NISHIMIYA ,  Toshikatsu ITOH ,  Teruyuki UEDA ,  Ryosuke GUNJI ,  Kengo HARA ,  Tohru DAITOH

IPC分类号： H01L27/12 ,  H01L29/417 ,  H01L29/423

摘要： An active matrix substrate includes a substrate, a TFT-containing layer which is supported on the substrate, and which includes a gate electrode, a gate insulating layer, a semiconductor layer, and source and drain electrodes of the TFT, a metal wiring layer which is supported on the substrate and has a thickness of 400 nm or more, and an inorganic insulating layer which is thinner than the metal wiring layer, and is arranged on a substrate side of the metal wiring layer and is in contact with a lower surface of the metal wiring layer. The metal wiring layer has tensile stress and the inorganic insulating layer has compressive stress, and a ratio Sb/Sa of an absolute value Sb of a stress value of the inorganic insulating layer to an absolute value Sa of a stress value of the metal wiring layer is 0.6 or more and 1.7 or less.

公开(公告)号：US20230100273A1

公开(公告)日：2023-03-30

申请号：US18076433

申请日：2022-12-07

申请人： Sharp Kabushiki Kaisha

发明人： Tetsuo KIKUCHI ,  Hideki KITAGAWA ,  Hajime IMAI ,  Toshikatsu ITOH ,  Masahiko SUZUKI ,  Teruyuki UEDA ,  Kengo HARA ,  Setsuji NISHIMIYA ,  Tohru DAITOH

IPC分类号： G09G3/36 ,  G02F1/1362 ,  H01L27/32

摘要： According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.

公开(公告)号：US20210305280A1

公开(公告)日：2021-09-30

申请号：US16497505

申请日：2018-03-26

申请人： Sharp Kabushiki Kaisha

发明人： Hideki KITAGAWA ,  Hajime IMAI ,  Toshikatsu ITOH ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Teruyuki UEDA ,  Kengo HARA ,  Setsuji NISHIMIYA ,  Tohru DAITOH

IPC分类号： H01L27/12 ,  G02F1/1362

摘要： There is provided a high-definition active matrix substrate while suppressing an occurrence of pixel defects. The active matrix substrate includes a first semiconductor film corresponding to one of two sub-pixels adjacent to each other in a row direction, a second semiconductor film corresponding to the other of two sub-pixels, a transistor using part of the first semiconductor film as a channel in the row direction, and a pixel electrode connected to a drain electrode of the transistor through a contact hole. In a plan view, a distance (dc) in the row direction from a drain electrode-side edge of the channel to a bottom surface of the contact hole is 0.15 or more times a sub-pixel pitch (dp) in the row direction.

公开(公告)号：US20210294138A1

公开(公告)日：2021-09-23

申请号：US16336483

申请日：2017-09-19

申请人： Sharp Kabushiki Kaisha

发明人： Hideki KITAGAWA ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Toshikatsu ITOH ,  Teruyuki UEDA ,  Setsuji NISHIMIYA ,  Kengo HARA

IPC分类号： G02F1/1368 ,  H01L27/12

摘要： A pixel area in the active matrix substrate 100 includes a thin film transistor 101 that has an oxide semiconductor layer 7, an inorganic insulating layer 11 and an organic insulating layer 12 that cover a thin film transistor, a common electrode 15, a dielectric layer 17 that primarily contains silicon nitride, and a pixel electrode 19. The inorganic insulating layer has a multi-layered structure that includes a silicon oxide layer and a silicon nitride layer. A pixel electrode 10 is brought into contact with a drain electrode 9 within a pixel contact hole. The pixel contact hole is configured with a first opening portion, a second opening portion, and a third opening portion that are formed in the inorganic insulating layer 11, the organic insulating layer 12, and the dielectric layer 17, respectively. A flank surface of the first opening portion and a flank surface of the second opening portion are aligned. The flank surface of the second opening portion includes a first portion 121 that is inclined at a first angle θ1 with respect to a substrate, a second portion 122 that is positioned above the first portion and is inclined at a second angle θ2 that is greater than the first angle, and a border 120 that is positioned between the first portion and the second portion and of which an inclination angle with respect to the substrate discontinuously changes.

公开(公告)号：US20190326443A1

公开(公告)日：2019-10-24

申请号：US16336481

申请日：2017-09-21

申请人： Sharp Kabushiki Kaisha

发明人： Masahiko SUZUKI ,  Hajime IMAI ,  Hideki KITAGAWA ,  Tetsuo KIKUCHI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Kengo HARA ,  Tohru DAITOH ,  Toshikatsu ITOH

IPC分类号： H01L29/786 ,  H01L29/24 ,  H01L21/02 ,  H01L29/66 ,  H01L27/12 ,  G02F1/1345 ,  G02F1/1368 ,  G02F1/1343

摘要： A semiconductor device includes a thin film transistor including a semiconductor layer, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, the semiconductor layer includes a layered structure including a first oxide semiconductor layer including In and Zn, in which an atomic ratio of In with respect to all metallic elements included in the first oxide semiconductor layer is higher than an atomic ratio of Zn, a second oxide semiconductor layer including In and Zn, in which an atomic ratio of Zn with respect to all metallic elements included in the second oxide semiconductor layer is higher than an atomic ratio of In, and an intermediate oxide semiconductor layer arranged between the first oxide semiconductor layer and the second oxide semiconductor layer, and the first and second oxide semiconductor layers are crystalline oxide semiconductor layers, and the intermediate oxide semiconductor layer is an amorphous oxide semiconductor layer, and the first oxide semiconductor layer is arranged nearer to the gate insulating layer than the second oxide semiconductor layer.

公开(公告)号：US20190072790A1

公开(公告)日：2019-03-07

申请号：US16055205

申请日：2018-08-06

申请人： Sharp Kabushiki Kaisha

发明人： Masaki MAEDA ,  Yoshihito HARA ,  Tohru DAITOH ,  Hajime IMAI ,  Hideki KITAGAWA ,  Toshikatsu ITOH ,  Tatsuya KAWASAKI

IPC分类号： G02F1/1333 ,  G02F1/1362 ,  H01L23/544 ,  H01L21/3213

摘要： A method of producing a substrate having an alignment mark includes a process of forming a lower layer side metal film on a substrate and forming a lower layer side alignment mark base having a lower layer side alignment mark that is a hole, a process of forming an upper layer side metal film on the substrate and the lower layer side metal film, a process of forming a photoresist film on the upper layer side metal film and forming a lower layer side alignment mark overlapping portion overlapping a part of the lower layer side alignment mark with patterning, an etching process of removing with etching selectively portions of the lower and upper layer side metal films not overlapping the lower layer side alignment mark overlapping portion and forming an upper layer side alignment mark that is the upper layer side metal film, and a photoresist removing process.

公开(公告)号：US20170358674A1

公开(公告)日：2017-12-14

申请号：US15531385

申请日：2015-11-19

申请人： Sharp Kabushiki Kaisha

发明人： Tetsuo KIKUCHI ,  Hajime IMAI ,  Hisao OCHI ,  Tetsuo FUJITA ,  Hideki KITAGAWA ,  Masahiko SUZUKI ,  Shingo KAWASHIMA ,  Tohru DAITOH

IPC分类号： H01L29/786 ,  H01L21/02 ,  G02F1/1362 ,  H01L21/28 ,  G02F1/1368 ,  H01L29/417 ,  G02F1/1333 ,  G02F1/1345

摘要： A semiconductor device includes a substrate and a thin film transistor supported by the substrate. The thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, and source and drain electrodes electrically connected to the oxide semiconductor layer. The gate insulating layer includes a first portion which is covered with the oxide semiconductor layer and a second portion which is adjacent to the first portion and which is not covered with any of the oxide semiconductor layer, the source electrode and the drain electrode. The second portion is smaller in thickness than the first portion, and the difference in thickness between the second portion and the first portion is more than 0 nm and not more than 50 nm.

公开(公告)号：US20230215876A1

公开(公告)日：2023-07-06

申请号：US18119624

申请日：2023-03-09

申请人： Sharp Kabushiki Kaisha

发明人： Masahiko SUZUKI ,  Tetsuo KIKUCHI ,  Hideki KITAGAWA ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Hitoshi TAKAHATA ,  Tohru DAITOH

IPC分类号： H01L27/12

CPC分类号： H01L27/124 ,  H01L27/1225

摘要： An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.