公开(公告)号：US12080710B2

公开(公告)日：2024-09-03

申请号：US17361418

申请日：2021-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyooho Jung ,  Young-Lim Park ,  Changmu An ,  Hongseon Song ,  Yukyung Shin

IPC: H01L27/08 ,  H01L49/02

CPC classification number: H01L27/0805 ,  H01L28/60

Abstract: Disclosed are semiconductor devices and fabrication methods for the same. The semiconductor devices may include a bottom electrode, a dielectric layer, and a top electrode that are sequentially stacked on a semiconductor substrate. The bottom electrode includes a first doping region in contact with the dielectric layer, a main region spaced apart from the dielectric layer by the first doping region intervening therebetween, and a second doping region between the first doping region and the main region. Each of the first and second doping regions includes oxygen and a doping metal. In some embodiments, the second doping region may include nitrogen. The main region may be devoid of the doping metal. An amount of oxygen in the second doping region is less than an amount of oxygen in the first doping region.

公开(公告)号：US12063772B2

公开(公告)日：2024-08-13

申请号：US18215301

申请日：2023-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyooho Jung ,  Yukyung Shin ,  Jinho Lee

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033

Abstract: A semiconductor device including a substrate; bottom electrodes on the substrate, each bottom electrode including a first region and a second region, the second region containing an additional element relative to the first region; a first supporting pattern on the substrate and in contact with a portion of a side surface of each bottom electrode; a top electrode on the bottom electrodes; a dielectric layer between the bottom electrodes and the top electrode; and a capping layer between the bottom electrodes and the dielectric layer, the capping layer covering a top surface and a bottom surface of the first supporting pattern, wherein the second region is in contact with the capping layer, and the capping layer and the dielectric layer include different materials from each other.

公开(公告)号：US20240224503A1

公开(公告)日：2024-07-04

申请号：US18542627

申请日：2023-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheoljin Cho ,  Yukyung Shin ,  Changhwa Jung ,  Jieun Lee ,  Jayun Choi

IPC: H10B12/00

CPC classification number: H10B12/315

Abstract: A semiconductor device includes a substrate, a first electrode disposed above the substrate, a multilayer dielectric structure configured to cover the first electrode, and a second electrode configured to cover the multilayer dielectric structure. The multilayer dielectric structure includes a plurality of dielectric films, a first dielectric film of the plurality of dielectric films includes crystalline TiO2 or crystalline SrTiO3, and a second dielectric film of the plurality of dielectric films is in contact with the first dielectric film and includes a high-k dielectric film having a tetragonal crystal structure.

公开(公告)号：US20240321938A1

公开(公告)日：2024-09-26

申请号：US18591310

申请日：2024-02-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheoljin Cho ,  Yukyung Shin ,  Jieun Lee ,  Hanjin Lim ,  Changhwa Jung ,  Jayun Choi

IPC: H10B12/00

CPC classification number: H01L28/55 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor device includes a lower electrode disposed on a substrate; a dielectric layer covering the lower electrode; and an upper electrode spaced apart from the lower electrode. The dielectric layer is disposed between the upper electrode and the lower electrode. A thickness of the dielectric layer is less than or equal to 6 nm, and a grain size in the dielectric layer is between 3 nm and 30 nm.

公开(公告)号：US11716840B2

公开(公告)日：2023-08-01

申请号：US17571935

申请日：2022-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyooho Jung ,  Yukyung Shin ,  Jinho Lee

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033 ,  H10B12/34

Abstract: A semiconductor device including a substrate; bottom electrodes on the substrate, each bottom electrode including a first region and a second region, the second region containing an additional element relative to the first region; a first supporting pattern on the substrate and in contact with a portion of a side surface of each bottom electrode; a top electrode on the bottom electrodes; a dielectric layer between the bottom electrodes and the top electrode; and a capping layer between the bottom electrodes and the dielectric layer, the capping layer covering a top surface and a bottom surface of the first supporting pattern, wherein the second region is in contact with the capping layer, and the capping layer and the dielectric layer include different materials from each other.

公开(公告)号：US20230209804A1

公开(公告)日：2023-06-29

申请号：US17935148

申请日：2022-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheoljin Cho ,  Yukyung Shin ,  Changhwa Jung ,  Hyunjun Kim ,  Hanjin Lim

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10823

Abstract: A capacitor is described. The capacitor includes a lower electrode, a dielectric layer structure disposed on the lower electrode, and an upper electrode disposed on the dielectric layer structure. The dielectric layer structure includes a first dielectric layer, a second dielectric layer contacting the first dielectric layer, and a third dielectric layer contacting the second dielectric layer. Each of the first to third dielectric layers includes a material with a crystalline structure. The second dielectric layer includes an oxide having ferroelectric or antiferroelectric properties, and the second dielectric layer includes a material in which at least two different crystal phases are mixed.