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公开(公告)号：US11797450B2
公开(公告)日：2023-10-24
申请号：US17232844
申请日：2021-04-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byoungsul Kim , Youngsan Kang , Daehyun Kwon , Myong-Seob Song , Byung Yo Lee , Yejin Jo
IPC: G06F12/0815 , G06F12/0804
CPC classification number: G06F12/0815 , G06F12/0804 , G06F2212/1032
Abstract: An electronic device includes a cache memory including a memory space for storing a first cache set including a plurality of sector data and a plurality of dirty bits, each of the plurality of dirty bits representing whether corresponding sector data of the plurality of sector data are modified, a memory controller, connected to a plurality of data lines and a data mask line, for receiving the plurality of sector data and the plurality of dirty bits from the cache memory, setting a logic level of a data mask signal based on a logic level of each of the plurality of dirty bits, and outputting the plurality of sector data through the plurality of data lines and the data mask signal through the data mask line, and a memory device, connected to the plurality of data lines and the data mask line, for receiving the plurality of sector data through the plurality of data lines, and receiving the data mask signal through the data mask line.
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2.发明公开公开(公告)号：US20230335209A1
公开(公告)日：2023-10-19
申请号：US17949000
申请日：2022-09-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngsan Kang , Donghee Kim , Jungho Jung , Jun-Ho Jo
CPC classification number: G11C29/36 , G11C29/12015 , G11C29/1201
Abstract: A semiconductor memory device includes: a memory core including memory cells and configured to output core data stored in the memory cells in response to a read request, a command decoder configured to decode at least one command input from an external device, a command log register configured to sequentially store the at least one command in response to a register enable signal and output the at least one command as a command log in response to a command log read signal, and a mode register set configured to generate the register enable signal or the command log read signal in response to a mode register set command transmitted to the command decoder.
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3.发明授权公开(公告)号：US11671287B2
公开(公告)日：2023-06-06
申请号：US17511186
申请日：2021-10-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngsan Kang , Byungyo Lee
CPC classification number: H04L25/03878 , H04L25/028 , H04L25/0292 , H04L25/03254 , H04L25/062
Abstract: An interconnect module device is provided. The interconnect module device includes a line control command (LCC) detecting circuit configured to identify an LCC signal; an equalizer control circuit configured to generate a control signal based on the LCC signal; a receiving equalizer configured to perform receiving equalization on a first signal received from a first universal flash storage (UFS) device based on the control signal to generate a second signal; and a transmitting equalizer configured to perform transmitting equalization on the second signal to generate a third signal based on the control signal, and transmit the third signal to a second UFS device.
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4.发明授权公开(公告)号：US12170121B2
公开(公告)日：2024-12-17
申请号：US17949000
申请日：2022-09-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngsan Kang , Donghee Kim , Jungho Jung , Jun-Ho Jo
Abstract: A semiconductor memory device includes: a memory core including memory cells and configured to output core data stored in the memory cells in response to a read request, a command decoder configured to decode at least one command input from an external device, a command log register configured to sequentially store the at least one command in response to a register enable signal and output the at least one command as a command log in response to a command log read signal, and a mode register set configured to generate the register enable signal or the command log read signal in response to a mode register set command transmitted to the command decoder.
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