公开(公告)号：US10606752B2

公开(公告)日：2020-03-31

申请号：US15890240

申请日：2018-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yingying Tian ,  Tarun Nakra ,  Khang Nguyen ,  Ravikanth Reddy ,  Edwin Silvera

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/128 ,  G06F12/0897 ,  G06F12/127

Abstract: Embodiments include a method and system for coordinating cache management for an exclusive cache hierarchy. The method and system may include managing, by a coordinated cache logic section, a level three (L3) cache, a level two (L2) cache, and/or a level one (L1) cache. Managing the L3 cache and the L2 cache may include coordinating a cache block replacement policy among the L3 cache and the L2 cache by filtering data with lower reuse probability from data with higher reuse probability. The method and system may include tracking reuse patterns of demand requests separately from reuse patterns of prefetch requests. Accordingly, a coordinated cache management policy may be built across multiple levels of a cache hierarchy, rather than a cache replacement policy within one cache level. Higher-level cache behavior may be used to guide lower-level cache allocation, bringing greater visibility of cache behavior to exclusive last level caches (LLCs).

公开(公告)号：US11609858B2

公开(公告)日：2023-03-21

申请号：US17402492

申请日：2021-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yingying Tian ,  Tarun Nakra ,  Vikas Sinha ,  Hien Le

IPC: G06F12/0888 ,  G06F12/128

Abstract: A system and a method to allocate data to a first cache increments a first counter if a reuse indicator for the data indicates that the data is likely to be reused and decremented the counter if the reuse indicator for the data indicates that the data is likely not to be reused. A second counter is incremented upon eviction of the data from the second cache, which is a higher level cache than the first cache. The data is allocated to the first cache if the value of the first counter is equal to or greater than the first predetermined threshold or the value of the second counter equals zero, and the data is bypassed from the first cache if the value of the first counter is less than the first predetermined threshold and the value of the second counter is not equal to zero.

公开(公告)号：US11113207B2

公开(公告)日：2021-09-07

申请号：US16289645

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yingying Tian ,  Tarun Nakra ,  Vikas Sinha ,  Hien Le

IPC: G06F12/123 ,  G06F9/50 ,  G06F12/0811 ,  G06F12/0888

Abstract: A system and a method to allocate data to a first cache increments a first counter if a reuse indicator for the data indicates that the data is likely to be reused and decremented the counter if the reuse indicator for the data indicates that the data is likely not to be reused. A second counter is incremented upon eviction of the data from the second cache, which is a higher level cache than the first cache. The data is allocated to the first cache if the value of the first counter is equal to or greater than the first predetermined threshold or the value of the second counter equals zero, and the data is bypassed from the first cache if the value of the first counter is less than the first predetermined threshold and the value of the second counter is not equal to zero.

公开(公告)号：US11055221B2

公开(公告)日：2021-07-06

申请号：US16424452

申请日：2019-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vikas Sinha ,  Hien Le ,  Tarun Nakra ,  Yingying Tian ,  Apurva Patel ,  Omar Torres

IPC: G06F12/08 ,  G06F12/0831 ,  G06F11/07 ,  G06F12/0868

Abstract: According to one general aspect, an apparatus may include a processor configured to issue a first request for a piece of data from a cache memory and a second request for the piece of data from a system memory. The apparatus may include the cache memory configured to temporarily store a subset of data. The apparatus may include a memory interconnect. The a memory interconnect may be configured to receive the second request for the piece of data from the system memory. The a memory interconnect may be configured to determine if the piece of memory is stored in the cache memory. The a memory interconnect may be configured to, if the piece of memory is determined to be stored in the cache memory, cancel the second request for the piece of data from the system memory.