公开(公告)号：US20170236751A1

公开(公告)日：2017-08-17

申请号：US15296202

申请日：2016-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong-Shin PARK ,  Young-Jae KIM

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522

CPC classification number: H01L21/76877 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76873 ,  H01L23/5226

Abstract: A method of fabricating a wiring structure for a semiconductor device may include forming a lower wiring in a lower insulating layer, forming an etch stop layer covering the lower insulating layer and the lower wiring, forming an interlayer insulating layer on the etch stop layer, forming a preliminary via-hole through the interlayer insulating layer, partially etching the interlayer insulating layer to form a trench partially merged with the preliminary via-hole and a via-hole defined by a remaining portion of the preliminary via-hole, removing the etch stop layer exposed by the via-hole to expose the lower wiring, partially etching a contact area at which the trench and the via-hole are in contact with each other and forming an upper wiring in the via-hole and the trench to be electrically connected to the lower wiring.