公开(公告)号：US11282695B2

公开(公告)日：2022-03-22

申请号：US16107942

申请日：2018-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Fan Chen ,  Weiyi Qi ,  Jongchol Kim ,  Jing Wang ,  Yang Lu ,  Woosung Choi

IPC: H01L21/02 ,  G06N3/08 ,  G06F9/30 ,  G06N3/04 ,  G06N3/12

Abstract: A system for reconstructing wafer maps of semiconductor wafers includes: a processor; and memory having instructions stored thereon that, when executed by the processor, cause the processor to: receive test data of a wafer at sparse sampling locations of the wafer, the sparse sampling locations being selected based on a probing mask; and compute a reconstructed wafer map by performing compressed sensing with Zernike polynomials on the test data at sparse locations of the wafer.

公开(公告)号：US20200082051A1

公开(公告)日：2020-03-12

申请号：US16390087

申请日：2019-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Uihui Kwon ,  Weiyi Qi ,  Yang Lu ,  Saetbyeol Ahn ,  Takeshi Okagaki

IPC: G06F17/50 ,  G06N20/00

Abstract: A standard cell design system is provided. The standard cell design system includes at least one processor configured to implement: a control engine that determines planar parameters and vertical parameters of a target standard cell, a three-dimensional structure generating engine that generates a three-dimensional structure of the target standard cell based on the planar parameters and the vertical parameters, an extraction engine that extracts a standard cell model of the target standard cell from the three-dimensional structure, an assessment engine that performs a plurality of assessment operations based on the standard cell model, and an auto-optimizing engine that adjusts, based on a machine learning algorithm, the planar parameters and the vertical parameters based on results of the plurality of assessment operations.

公开(公告)号：US20190096659A1

公开(公告)日：2019-03-28

申请号：US16107942

申请日：2018-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Fan Chen ,  Weiyi Qi ,  Jongchol Kim ,  Jing Wang ,  Yang Lu ,  Woosung Choi

IPC: H01L21/02 ,  G06F9/30 ,  G06N3/08

Abstract: A system for reconstructing wafer maps of semiconductor wafers includes: a processor; and memory having instructions stored thereon that, when executed by the processor, cause the processor to: receive test data of a wafer at sparse sampling locations of the wafer, the sparse sampling locations being selected based on a probing mask; and compute a reconstructed wafer map by performing compressed sensing with Zernike polynomials on the test data at sparse locations of the wafer.

公开(公告)号：US10796068B2

公开(公告)日：2020-10-06

申请号：US16390087

申请日：2019-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Uihui Kwon ,  Weiyi Qi ,  Yang Lu ,  Saetbyeol Ahn ,  Takeshi Okagaki

IPC: G06F30/398 ,  G06N20/00 ,  G06F30/392 ,  G06F119/18

Abstract: A standard cell design system is provided. The standard cell design system includes at least one processor configured to implement: a control engine that determines planar parameters and vertical parameters of a target standard cell, a three-dimensional structure generating engine that generates a three-dimensional structure of the target standard cell based on the planar parameters and the vertical parameters, an extraction engine that extracts a standard cell model of the target standard cell from the three-dimensional structure, an assessment engine that performs a plurality of assessment operations based on the standard cell model, and an auto-optimizing engine that adjusts, based on a machine learning algorithm, the planar parameters and the vertical parameters based on results of the plurality of assessment operations.