公开(公告)号：US11664331B2

公开(公告)日：2023-05-30

申请号：US17466323

申请日：2021-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul Woo Kim ,  Sang Min Yong ,  Yang Gyoo Jung

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/16

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L25/0655

Abstract: A semiconductor package is provided. The semiconductor package comprises a first substrate, a second substrate disposed on the first substrate, a first semiconductor chip disposed on the second substrate, and a stiffener extending from an upper surface of the first substrate to an upper surface of the second substrate, the stiffener not being in contact with the first semiconductor chip, wherein a first height from the upper surface of the first substrate to an upper surface of the first semiconductor chip is greater than a second height from the upper surface of the first substrate to an uppermost surface of the stiffener.

公开(公告)号：US11139253B2

公开(公告)日：2021-10-05

申请号：US16583335

申请日：2019-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chui Woo Kim ,  Sang Min Yong ,  Yang Gyoo Jung

IPC: H01L23/16 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package is provided. The semiconductor package comprises a first substrate, a second substrate disposed on the first substrate, a first semiconductor chip disposed on the second substrate, and a stiffener extending from an upper surface of the first substrate to an upper surface of the second substrate, the stiffener not being in contact with the first semiconductor chip, wherein a first height from the upper surface of the first substrate to an upper surface of the first semiconductor chip is greater than a second height from the upper surface of the first substrate to an uppermost surface of the stiffener.

公开(公告)号：US11217503B2

公开(公告)日：2022-01-04

申请号：US16748061

申请日：2020-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yang Gyoo Jung ,  Chul Woo Kim ,  Hyo-Chang Ryu ,  Seung-Kwan Ryu ,  Yun Seok Choi

IPC: H01L23/367 ,  H01L23/42 ,  H01L25/10 ,  H01L25/065 ,  H01L23/498 ,  H05K1/18 ,  H01L23/00

Abstract: A semiconductor package includes a substrate and an interposer disposed on the substrate. The interposer comprises a first surface facing the substrate and a second surface facing away from the substrate. A first logic semiconductor chip is disposed on the first surface of the interposer and is spaced apart from the substrate in a first direction orthogonal to an upper surface of the substrate. A first memory package is disposed on the second surface of the interposer. A second memory package is disposed on the second surface of the interposer and is spaced apart from the first memory package in a second direction that is parallel to the upper surface of the substrate. A first heat transfer unit is disposed on a surface of the substrate facing the first logic semiconductor chip. The first heat transfer unit is spaced apart from the first logic semiconductor chip in the first direction.