公开(公告)号：US20220344514A1

公开(公告)日：2022-10-27

申请号：US17862961

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： WEONHONG KIM ,  WANDON KIM ,  HYEONJUN BAEK ,  SANGJIN HYUN

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786 ,  H01L21/28

Abstract: A semiconductor device includes a substrate including an active pattern, a gate electrode crossing the active pattern in a plan view, and a ferroelectric pattern interposed between the active pattern and the gate electrode. The gate electrode includes a work function metal pattern disposed on the ferroelectric pattern, and an electrode pattern filling a recess formed in an upper portion of the work function metal pattern. A top surface of a topmost portion of the ferroelectric pattern is lower than a bottom surface of the recess.

公开(公告)号：US20200013898A1

公开(公告)日：2020-01-09

申请号：US16458412

申请日：2019-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGHYUK YIM ,  WANDON KIM ,  WEONHONG KIM ,  JONGHO PARK ,  HYEONJUN BAEK ,  BYOUNGHOON LEE ,  SANGJIN HYUN

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08

Abstract: A semiconductor device includes a substrate including first and second active regions, first and second active patterns disposed on the first and second active regions, respectively, first and second gate electrodes crossing the first and second active patterns, respectively, a first gate insulating pattern interposed between the first active pattern and the first gate electrode, and a second gate insulating pattern interposed between the second active pattern and the second gate electrode. The first gate insulating pattern includes a first dielectric pattern and a first ferroelectric pattern disposed on the first dielectric pattern. The second gate insulating pattern includes a second dielectric pattern. A threshold voltage of a transistor in the first active region is different from a threshold voltage of a transistor in the second active region.

公开(公告)号：US20210020628A1

公开(公告)日：2021-01-21

申请号：US16817069

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGHA OH ,  PIL-KYU KANG ,  KUGHWAN KIM ,  WEONHONG KIM ,  YUICHIRO SASAKI ,  SANG WOO LEE ,  SUNGKEUN LIM ,  YONGHO HA ,  SANGJIN HYUN

IPC: H01L27/06 ,  H01L27/11578 ,  H01L27/11558 ,  H01L27/24 ,  H01L23/48

Abstract: A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).

公开(公告)号：US20210167214A1

公开(公告)日：2021-06-03

申请号：US17176248

申请日：2021-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： WEONHONG KIM ,  WANDON KIM ,  HYEONJUN BAEK ,  SANGJIN HYUN

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

Abstract: A semiconductor device includes a substrate including an active pattern, a gate electrode crossing the active pattern in a plan view, and a ferroelectric pattern interposed between the active pattern and the gate electrode. The gate electrode includes a work function metal pattern disposed on the ferroelectric pattern, and an electrode pattern filling a recess formed in an upper portion of the work function metal pattern. A top surface of a topmost portion of the ferroelectric pattern is lower than a bottom surface of the recess.

公开(公告)号：US20200013899A1

公开(公告)日：2020-01-09

申请号：US16503790

申请日：2019-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： WEONHONG KIM ,  WANDON KIM ,  HYEONJUN BAEK ,  SANGJIN HYUN

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including an active pattern, a gate electrode crossing the active pattern in a plan view, and a ferroelectric pattern interposed between the active pattern and the gate electrode. The gate electrode includes a work function metal pattern disposed on the ferroelectric pattern, and an electrode pattern filling a recess formed in an upper portion of the work function metal pattern. A top surface of a topmost portion of the ferroelectric pattern is lower than a bottom surface of the recess.