公开(公告)号：US20190311953A1

公开(公告)日：2019-10-10

申请号：US16185213

申请日：2018-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： NAMGYU CHO ,  KUGHWAN KIM ,  GEUNWOO KIM ,  JUNGMIN PARK ,  MINWOO SONG

IPC: H01L21/8234 ,  H01L29/40 ,  H01L29/66 ,  H01L21/3213

Abstract: A method of fabricating a semiconductor device may include forming a first conductive layer on first to third regions of a substrate, forming a barrier layer on the first conductive layer, the barrier layer including a first barrier layer, a second barrier layer, and a sacrificial layer which are sequentially formed, sequentially forming a second conductive layer and a third conductive layer on the barrier layer, performing a first etching process to remove the third conductive layer from the second region and the third region, the third conductive layer remaining on the first region after the first etching process, and performing a second etching process to remove the second conductive layer and the sacrificial layer from the third region, the second conductive layer and the sacrificial layer remaining on the first region and on the second region after the second etching process.

公开(公告)号：US20210020628A1

公开(公告)日：2021-01-21

申请号：US16817069

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGHA OH ,  PIL-KYU KANG ,  KUGHWAN KIM ,  WEONHONG KIM ,  YUICHIRO SASAKI ,  SANG WOO LEE ,  SUNGKEUN LIM ,  YONGHO HA ,  SANGJIN HYUN

IPC: H01L27/06 ,  H01L27/11578 ,  H01L27/11558 ,  H01L27/24 ,  H01L23/48

Abstract: A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).