公开(公告)号：US10649681B2

公开(公告)日：2020-05-12

申请号：US15133205

申请日：2016-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhas ,  Ashwini Batrahalli ,  Tameesh Suri

IPC: H04L29/08 ,  G06F3/06

Abstract: A Solid State Drive (SSD) (110) is disclosed. The SSD (110) may include storage (218) for data, and reception circuitry (203) to receive various instructions and data. The reception circuitry (203) may receive an instruction (257) from a host machine (105) to perform garbage collection, along with a selected P/E strategy (260). The SSD (110) may include garbage collection logic (209) to perform garbage collection, possibly with a delayed Program operation if an adaptive P/E strategy (1110) is selected. The SSD (110) may also include a mapping table (221) that may identify which pages were not Programmed before victim blocks (233, 236) were erased, and therefore require replication during a delayed Program operation.

公开(公告)号：US11314441B2

公开(公告)日：2022-04-26

申请号：US16875986

申请日：2020-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Narges Shahidi ,  Manu Awasthi ,  Tameesh Suri ,  Vijay Balakrishnan

IPC: G06F3/06

Abstract: According to one general aspect, an apparatus may include a memory, an erasure-based, non-volatile memory, and a processor. The memory may be configured to store a mapping table, wherein the mapping table indicates a rewriteable state of a plurality of memory addresses. The erasure-based, non-volatile memory may be configured to store information, at respective memory addresses, in an encoded format. The encoded format may include more bits than the unencoded version of the information and the encoded format may allow the information be over-written, at least once, without an intervening erase operation. The processor may be configured to perform garbage collection based, at least in part upon, the rewriteable state associated with the respective memory addresses.

公开(公告)号：US20160188534A1

公开(公告)日：2016-06-30

申请号：US14674399

申请日：2015-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tameesh Suri ,  Manu Awasthi ,  Mrinmoy Ghosh

IPC: G06F15/82 ,  G06F9/44 ,  G06F9/50

CPC classification number: G06F9/4403 ,  G06F9/4411 ,  G06F9/5016 ,  G06F12/0646

Abstract: A computing system includes: an identification block configured to determine a structural profile for representing a parallel structure of architectural components; and an arrangement block, coupled to the identification block, configured to generate memory sets based on the structural profile for representing the parallel structure.

Abstract translation: 计算系统包括：识别块，被配置为确定用于表示架构组件的并行结构的结构简档; 以及耦合到所述识别块的配置块，被配置为基于用于表示所述并行结构的所述结构轮廓来生成存储器组。

公开(公告)号：US10671317B2

公开(公告)日：2020-06-02

申请号：US15405227

申请日：2017-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Narges Shahidi ,  Manu Awasthi ,  Tameesh Suri ,  Vijay Balakrishnan

IPC: G06F3/06

Abstract: According to one general aspect, an apparatus may include a memory, an erasure-based, non-volatile memory, and a processor. The memory may be configured to store a mapping table, wherein the mapping table indicates a rewriteable state of a plurality of memory addresses. The erasure-based, non-volatile memory may be configured to store information, at respective memory addresses, in an encoded format. The encoded format may include more bits than the unencoded version of the information and the encoded format may allow the information be over-written, at least once, without an intervening erase operation. The processor may be configured to perform garbage collection based, at least in part upon, the rewriteable state associated with the respective memory addresses.

公开(公告)号：US10474567B2

公开(公告)日：2019-11-12

申请号：US15217964

申请日：2016-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Narges Shahidi ,  Tameesh Suri ,  Manu Awasthi ,  Vijay Balakrishnan

IPC: G06F12/02

Abstract: According to one general aspect, an apparatus may include a host interface, a memory, a processor, and an erasure-based, non-volatile memory. The host interface may receive a write command, wherein the write command includes unencoded data. The memory may store a mapping table, wherein the mapping table indicates a rewriteable state of a plurality of memory addresses. The processor may select a memory address to store information included by the unencoded data based, at least in part, upon the rewriteable state of the memory address. The erasure-based, non-volatile memory may store, at the memory address, the unencoded data's information as encoded data, wherein the encoded data includes more bits than the unencoded data and wherein the encoded data can be over-written with a second unencoded data without an intervening erase operation.

公开(公告)号：US09723071B2

公开(公告)日：2017-08-01

申请号：US14595172

申请日：2015-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tameesh Suri ,  Manu Awasthi

IPC: G06F15/16 ,  H04L29/08 ,  H04L12/801

CPC classification number: H04L67/104 ,  H04L47/193 ,  H04L67/2842 ,  H04L69/321

Abstract: Inventive aspects include a high bandwidth peer-to-peer switched key-value system, method, and section. The system can include a high bandwidth switch, multiple network interface cards communicatively coupled to the switch, one or more key-value caches to store a plurality of key-values, and one or more memory controllers communicatively coupled to the key-value caches and to the network interface cards. The memory controllers can include a key-value peer-to-peer logic section that can coordinate peer-to-peer communication between the memory controllers and the multiple network interface cards through the switch. The system can further include multiple transmission control protocol (TCP) offload engines that are each communicatively coupled to a corresponding one of the network interface cards. Each of the TCP offload engines can include a packet peer-to-peer logic section that can coordinate the peer-to-peer communication between the memory controllers and the network interface cards through the switch.