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    Data management scheme in virtualized hyperscale environments
    1.
    发明授权
    Data management scheme in virtualized hyperscale environments 有权

    公开(公告)号：US10725663B2

    公开(公告)日：2020-07-28

    申请号：US16231229

    申请日：2018-12-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Manu Awasthi ,  Robert Brennan

    IPC: G06F3/06

    Abstract: According to one general aspect, a memory management unit (MMU) may be configured to interface with a heterogeneous memory system that comprises a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with performance characteristic(s). The MMU may receive a data access for the heterogeneous memory system. The MMU may also determine at least one of the storage mediums of the heterogeneous memory system to service the data access. The target storage medium may be selected based upon at least one performance characteristic associated with the target storage medium and a quality of service tag that is associated with the virtual machine and that indicates one or more performance characteristics. The MMU may route the data access by the virtual machine to the at least one of the storage mediums.

    Block cleanup: page reclamation process to reduce garbage collection overhead in dual-programmable NAND flash devices
    2.
    发明授权
    Block cleanup: page reclamation process to reduce garbage collection overhead in dual-programmable NAND flash devices 有权

    公开(公告)号：US11314441B2

    公开(公告)日：2022-04-26

    申请号：US16875986

    申请日：2020-05-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Narges Shahidi ,  Manu Awasthi ,  Tameesh Suri ,  Vijay Balakrishnan

    IPC: G06F3/06

    Abstract: According to one general aspect, an apparatus may include a memory, an erasure-based, non-volatile memory, and a processor. The memory may be configured to store a mapping table, wherein the mapping table indicates a rewriteable state of a plurality of memory addresses. The erasure-based, non-volatile memory may be configured to store information, at respective memory addresses, in an encoded format. The encoded format may include more bits than the unencoded version of the information and the encoded format may allow the information be over-written, at least once, without an intervening erase operation. The processor may be configured to perform garbage collection based, at least in part upon, the rewriteable state associated with the respective memory addresses.

    RACK-LEVEL SCHEDULING FOR REDUCING THE LONG TAIL LATENCY USING HIGH PERFORMANCE SSDS
    5.
    发明申请
    RACK-LEVEL SCHEDULING FOR REDUCING THE LONG TAIL LATENCY USING HIGH PERFORMANCE SSDS 审中-公开

    公开(公告)号：US20200225999A1

    公开(公告)日：2020-07-16

    申请号：US16828649

    申请日：2020-03-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Qiumin Xu ,  Krishna Malladi ,  Manu Awasthi

    IPC: G06F9/50

    Abstract: A method for migrating a workload includes: receiving workloads generated from a plurality of applications running in a plurality of server nodes of a rack system; monitoring latency requirements for the workloads and detecting a violation of the latency requirement for a workload; collecting system utilization information of the rack system; calculating rewards for migrating the workload to other server nodes in the rack system; determining a target server node among the plurality of server nodes that maximizes the reward; and performing migration of the workload to the target server node.

    Block cleanup: page reclamation process to reduce garbage collection overhead in dual-programmable NAND flash devices
    6.
    发明授权
    Block cleanup: page reclamation process to reduce garbage collection overhead in dual-programmable NAND flash devices 审中-公开

    公开(公告)号：US10671317B2

    公开(公告)日：2020-06-02

    申请号：US15405227

    申请日：2017-01-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Narges Shahidi ,  Manu Awasthi ,  Tameesh Suri ,  Vijay Balakrishnan

    IPC: G06F3/06

    Abstract: According to one general aspect, an apparatus may include a memory, an erasure-based, non-volatile memory, and a processor. The memory may be configured to store a mapping table, wherein the mapping table indicates a rewriteable state of a plurality of memory addresses. The erasure-based, non-volatile memory may be configured to store information, at respective memory addresses, in an encoded format. The encoded format may include more bits than the unencoded version of the information and the encoded format may allow the information be over-written, at least once, without an intervening erase operation. The processor may be configured to perform garbage collection based, at least in part upon, the rewriteable state associated with the respective memory addresses.

    Multi-bit data representation framework to enable dual program operation on solid-state flash devices
    7.
    发明授权
    Multi-bit data representation framework to enable dual program operation on solid-state flash devices 有权

    公开(公告)号：US10474567B2

    公开(公告)日：2019-11-12

    申请号：US15217964

    申请日：2016-07-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Narges Shahidi ,  Tameesh Suri ,  Manu Awasthi ,  Vijay Balakrishnan

    IPC: G06F12/02

    Abstract: According to one general aspect, an apparatus may include a host interface, a memory, a processor, and an erasure-based, non-volatile memory. The host interface may receive a write command, wherein the write command includes unencoded data. The memory may store a mapping table, wherein the mapping table indicates a rewriteable state of a plurality of memory addresses. The processor may select a memory address to store information included by the unencoded data based, at least in part, upon the rewriteable state of the memory address. The erasure-based, non-volatile memory may store, at the memory address, the unencoded data's information as encoded data, wherein the encoded data includes more bits than the unencoded data and wherein the encoded data can be over-written with a second unencoded data without an intervening erase operation.

    Data management scheme in virtualized hyperscale environments
    9.
    发明授权
    Data management scheme in virtualized hyperscale environments 有权

    公开(公告)号：US11966581B2

    公开(公告)日：2024-04-23

    申请号：US16897264

    申请日：2020-06-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Manu Awasthi ,  Robert Brennan

    IPC: G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/0631 ,  G06F3/0685

    Abstract: According to one general aspect, a memory management unit (MMU) may be configured to interface with a heterogeneous memory system that comprises a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with performance characteristic(s). The MMU may receive a data access for the heterogeneous memory system. The MMU may also determine at least one of the storage mediums of the heterogeneous memory system to service the data access. The target storage medium may be selected based upon at least one performance characteristic associated with the target storage medium and a quality of service tag that is associated with the virtual machine and that indicates one or more performance characteristics. The MMU may route the data access by the virtual machine to the at least one of the storage mediums.

    Rack-level scheduling for reducing the long tail latency using high performance SSDs
    10.
    发明授权
    Rack-level scheduling for reducing the long tail latency using high performance SSDs 有权

    公开(公告)号：US11507435B2

    公开(公告)日：2022-11-22

    申请号：US16828649

    申请日：2020-03-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Qiumin Xu ,  Krishna Malladi ,  Manu Awasthi

    IPC: G06F9/46 ,  G06F9/50

    Abstract: A method for migrating a workload includes: receiving workloads generated from a plurality of applications running in a plurality of server nodes of a rack system; monitoring latency requirements for the workloads and detecting a violation of the latency requirement for a workload; collecting system utilization information of the rack system; calculating rewards for migrating the workload to other server nodes in the rack system; determining a target server node among the plurality of server nodes that maximizes the reward; and performing migration of the workload to the target server node.

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