公开(公告)号：US08691682B2

公开(公告)日：2014-04-08

申请号：US13775496

申请日：2013-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tai-Soo Lim ,  HyunSeok Lim ,  Shin-Jae Kang ,  Kyung-Tae Jang

IPC: H01L21/00

CPC classification number: H01L27/11578 ,  H01L21/28556 ,  H01L21/76879 ,  H01L23/485 ,  H01L27/11582 ,  H01L27/24 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  H01L45/04 ,  H01L45/145 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.

Abstract translation: 形成半导体器件的方法包括在半导体结构上形成绝缘层，在绝缘层中形成开口，该开口具有由绝缘层的一侧限定的侧壁，在开口中形成第一金属层，至少部分地 通过对第一金属层进行湿蚀刻工艺，并且在蚀刻的第一金属层上选择性地形成第二金属层，使开口的侧壁暴露。 第一金属层的平均粒径小于第二金属层的平均粒径。 还公开了相关的半导体器件。

公开(公告)号：US09711523B2

公开(公告)日：2017-07-18

申请号：US14574456

申请日：2014-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggil Lee ,  Yeon-Sil Sohn ,  Woonghee Sohn ,  Kihyun Yoon ,  Myoungbum Lee ,  Tai-Soo Lim ,  Yong Chae Jung

IPC: H01L27/11582

CPC classification number: H01L27/11582

Abstract: Provided is a semiconductor device, including gate structures on a substrate, the gate structures extending parallel to a first direction and being spaced apart from each other by a separation trench interposed therebetween, each of the gate structures including insulating patterns stacked on the substrate and a gate electrode interposed therebetween; vertical pillars connected to the substrate through the gate structures; an insulating spacer in the separation trench covering a sidewall of each of the gate structures; and a diffusion barrier structure between the gate electrode and the insulating spacer.

公开(公告)号：US20130164928A1

公开(公告)日：2013-06-27

申请号：US13775496

申请日：2013-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tai-Soo Lim ,  HyunSeok Lim ,  Shin-Jae Kang ,  Kyung-Tae Jang

IPC: H01L21/28

CPC classification number: H01L27/11578 ,  H01L21/28556 ,  H01L21/76879 ,  H01L23/485 ,  H01L27/11582 ,  H01L27/24 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  H01L45/04 ,  H01L45/145 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.

Abstract translation: 形成半导体器件的方法包括在半导体结构上形成绝缘层，在绝缘层中形成开口，该开口具有由绝缘层的一侧限定的侧壁，在开口中形成第一金属层，至少部分地 通过对第一金属层进行湿蚀刻工艺，并且在蚀刻的第一金属层上选择性地形成第二金属层，使开口的侧壁暴露。 第一金属层的平均粒径小于第二金属层的平均粒径。 还公开了相关的半导体器件。