公开(公告)号：US20130164928A1

公开(公告)日：2013-06-27

申请号：US13775496

申请日：2013-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tai-Soo Lim ,  HyunSeok Lim ,  Shin-Jae Kang ,  Kyung-Tae Jang

IPC: H01L21/28

CPC classification number: H01L27/11578 ,  H01L21/28556 ,  H01L21/76879 ,  H01L23/485 ,  H01L27/11582 ,  H01L27/24 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  H01L45/04 ,  H01L45/145 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.

Abstract translation: 形成半导体器件的方法包括在半导体结构上形成绝缘层，在绝缘层中形成开口，该开口具有由绝缘层的一侧限定的侧壁，在开口中形成第一金属层，至少部分地 通过对第一金属层进行湿蚀刻工艺，并且在蚀刻的第一金属层上选择性地形成第二金属层，使开口的侧壁暴露。 第一金属层的平均粒径小于第二金属层的平均粒径。 还公开了相关的半导体器件。

公开(公告)号：US09312270B2

公开(公告)日：2016-04-12

申请号：US14593221

申请日：2015-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Tae Jang ,  Myoungbum Lee ,  Seungmok Shin ,  JinGyun Kim ,  Yeon-Sil Sohn ,  Seung-Yup Lee ,  Dae-Hun Choi

IPC: H01L21/00 ,  H01L27/115 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/8239 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582

Abstract: Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm2 to about 10×109 dyne/cm2 to the substrate and the second material layer applies a stress in a range of about −0.1×109 dyne/cm2 to about −10×109 dyne/cm2 to the substrate.

Abstract translation: 提供制造三维半导体器件的方法。 该方法包括：在基板上形成薄膜结构，其中至少2n（n是大于2的整数）的第一和第二材料层交替重复堆叠; 其中所述第一材料层向所述基板施加约0.1×10 9达因/ cm 2至约10×10 9达因/ cm 2的范围内的应力，并且所述第二材料层施加约-0.1×109达因/ cm2的范围内的应力 至约-10×109达因/平方厘米。

公开(公告)号：US09184178B2

公开(公告)日：2015-11-10

申请号：US14564364

申请日：2014-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Tae Jang ,  Myoung-Bum Lee ,  Ji-Youn Seo ,  Chang-Won Lee ,  Yong-Chae Jung ,  Woong-Hee Sohn

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.

Abstract translation: 半导体器件包括衬底，垂直堆叠在衬底上的多个绝缘层，多个通道，布置在通过多个绝缘层中的至少一些形成的垂直开口中，以及多个部分交替地与多个绝缘体 层在垂直方向。 这些部分中的至少一些是相邻的多个通道的相应通道。 每个部分包括形成在该部分的内壁上的导电阻挡图案，位于导电阻挡图案上的部分中的填充层图案，以及位于未被导电屏障占据部分的剩余区域中的栅电极 或填充层图案。

公开(公告)号：US20150091078A1

公开(公告)日：2015-04-02

申请号：US14564364

申请日：2014-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Tae Jang ,  Myoung-Bum Lee ,  Ji-Youn Seo ,  Chang-Won Lee ,  Yong-Chae Jung ,  Woong-Hee Sohn

IPC: H01L27/115 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.

Abstract translation: 半导体器件包括衬底，垂直堆叠在衬底上的多个绝缘层，多个通道，布置在通过多个绝缘层中的至少一些形成的垂直开口中，以及多个部分交替地与多个绝缘体 层在垂直方向。 这些部分中的至少一些是相邻的多个通道的相应通道。 每个部分包括形成在该部分的内壁上的导电阻挡图案，位于导电阻挡图案上的部分中的填充层图案，以及位于未被导电屏障占据部分的剩余区域中的栅电极 或填充层图案。

公开(公告)号：US08691682B2

公开(公告)日：2014-04-08

申请号：US13775496

申请日：2013-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tai-Soo Lim ,  HyunSeok Lim ,  Shin-Jae Kang ,  Kyung-Tae Jang

IPC: H01L21/00

CPC classification number: H01L27/11578 ,  H01L21/28556 ,  H01L21/76879 ,  H01L23/485 ,  H01L27/11582 ,  H01L27/24 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  H01L45/04 ,  H01L45/145 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.

Abstract translation: 形成半导体器件的方法包括在半导体结构上形成绝缘层，在绝缘层中形成开口，该开口具有由绝缘层的一侧限定的侧壁，在开口中形成第一金属层，至少部分地 通过对第一金属层进行湿蚀刻工艺，并且在蚀刻的第一金属层上选择性地形成第二金属层，使开口的侧壁暴露。 第一金属层的平均粒径小于第二金属层的平均粒径。 还公开了相关的半导体器件。