公开(公告)号：US20170062038A1

公开(公告)日：2017-03-02

申请号：US15065211

申请日：2016-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su-Yeon DOO ,  Tae-Young OH ,  Kwang-Il PARK

IPC: G11C11/406

CPC classification number: G06F13/1636 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/40615

Abstract: A memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a plurality of dynamic memory cells. The memory controller controls the semiconductor memory device. The memory controller applies an auto-refresh command to the semiconductor memory device at each refresh interval of the semiconductor memory device such that the semiconductor memory performs a refresh operation in a normal mode, and does not apply the auto-refresh command to the semiconductor memory device during a self-refresh interval in which the semiconductor memory performs a self-refresh operation. After the semiconductor memory device exits from the self-refresh interval, the memory controller adjusts an application of the auto-refresh command in the normal mode by reflecting information of the self-refresh interval.

Abstract translation: 存储器系统包括半导体存储器件和存储器控制器。 半导体存储器件包括多个动态存储单元。 存储器控制器控制半导体存储器件。 存储器控制器在半导体存储器件的每个刷新间隔处向半导体存储器件施加自动刷新命令，使得半导体存储器以正常模式执行刷新操作，并且不将自动刷新命令应用于半导体存储器 在自刷新间隔期间，半导体存储器执行自刷新操作。 在半导体存储器件退出自刷新间隔之后，存储器控制器通过反映自刷新间隔的信息来调整在正常模式下的自动刷新命令的应用。

公开(公告)号：US20150250020A1

公开(公告)日：2015-09-03

申请号：US14633483

申请日：2015-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Hwan LEE ,  Tae-Young OH ,  Il-Pyo HONG ,  Seong-Won SON ,  Tae-Sin SONG

IPC: H04W88/06 ,  H04W36/00 ,  H04B7/06

CPC classification number: H04W88/06 ,  H04B7/06 ,  H04W36/0022

Abstract: An apparatus and method for providing an LTE service in an electronic device. The method includes: transmitting or receiving a voice signal through a first antenna and a data signal through a second antenna when the electronic device provides a multi-communication service. At least one switch connects at least one antenna and at least one communication interface with each other. When the electronic device provides a single communication service, transmitting or receiving a data signal or a voice signal through the first antenna, using the at least one switch.

Abstract translation: 一种用于在电子设备中提供LTE服务的装置和方法。 该方法包括：当电子设备提供多通信服务时，通过第一天线通过第二天线发送或接收语音信号和数据信号。 至少一个开关将至少一个天线和至少一个通信接口彼此连接起来。 当电子设备提供单个通信服务时，使用至少一个开关通过第一天线发送或接收数据信号或语音信号。

公开(公告)号：US20220351764A1

公开(公告)日：2022-11-03

申请号：US17862718

申请日：2022-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun SHIN ,  Tae-Young OH

IPC: G11C8/06 ,  G11C8/18 ,  G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G06F3/06 ,  G11C11/4076 ,  G06F13/16

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US20190065050A1

公开(公告)日：2019-02-28

申请号：US16169178

申请日：2018-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun SHIN ,  Tae-Young OH

IPC: G06F3/06 ,  G11C11/4076 ,  G11C7/10 ,  G06F13/16 ,  G11C8/10 ,  G11C8/18 ,  G11C7/22 ,  G11C8/06

CPC classification number: G06F3/06 ,  G06F13/1689 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/22 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US20140032826A1

公开(公告)日：2014-01-30

申请号：US13941359

申请日：2013-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-Jin LEE ,  Dae-Hyun KIM ,  Seung-Jun BAE ,  Young-Soo SOHN ,  Tae-Young OH

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G06F9/4403 ,  G11C11/40 ,  G11C11/4072 ,  G11C29/028 ,  G11C2029/4402

Abstract: A method of training a memory device included in a memory system is provided. The method includes testing memory core parameters for a memory core of the memory device during a booting-up sequence of the memory system; determining trimmed memory core parameters based on the test results; storing the determined trimmed memory core parameters; and applying the trimmed memory core parameter to the memory device during a normal operation of the memory device.

Abstract translation: 提供了一种训练包括在存储器系统中的存储器件的方法。 该方法包括在存储器系统的引导序列期间测试存储器件的存储器核心的存储器核心参数; 根据测试结果确定修剪内存核心参数; 存储所确定的修整的存储器核心参数; 以及在存储器件的正常操作期间将修整的存储器核心参数应用于存储器件。

公开(公告)号：US20170110177A1

公开(公告)日：2017-04-20

申请号：US15194784

申请日：2016-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Ho LEE ,  Seung-Jun SHIN ,  Tae-Young OH

IPC: G11C11/406 ,  G06F3/06

CPC classification number: G11C11/40615 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0683 ,  G11C11/40618

Abstract: A memory device includes a memory bank including a plurality of memory blocks, a row selection circuit and a refresh controller. The row selection circuit is configured to perform an access operation and a refresh operation with respect to the memory bank. The refresh controller is configured to control the row selection circuit such that the memory device is operated selectively in an access mode or a self-refresh mode in response to a self-refresh command received from a memory controller, the refresh operation is performed in the access mode in response to an active command received from the memory controller and the refresh operation is performed in the self-refresh mode in response to at least one clock signal.

公开(公告)号：US20230410863A1

公开(公告)日：2023-12-21

申请号：US18238232

申请日：2023-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun SHIN ,  Tae-Young OH

IPC: G11C8/06 ,  G11C8/18 ,  G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G06F3/06 ,  G11C11/4076 ,  G06F13/16

CPC classification number: G11C8/06 ,  G11C8/18 ,  G11C8/10 ,  G11C7/22 ,  G11C7/1057 ,  G06F3/06 ,  G11C7/1045 ,  G11C11/4076 ,  G06F13/1689 ,  G11C7/10

Abstract: A memory system, including a memory controller and a memory, wherein the memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller mixes a second command with the first command and transmits the mixture of the first command and the second command. The memory changes command latch timing depends on the first or second mode.

公开(公告)号：US20170365309A1

公开(公告)日：2017-12-21

申请号：US15690379

申请日：2017-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun SHIN ,  Tae-Young OH

IPC: G11C7/22 ,  G11C8/18 ,  G11C7/10 ,  G06F3/06 ,  G11C8/06 ,  G11C11/4076 ,  G11C8/10

CPC classification number: G06F3/06 ,  G06F13/1689 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/22 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US20170110169A1

公开(公告)日：2017-04-20

申请号：US15187967

申请日：2016-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Ran KIM ,  Tae-Young OH

IPC: G11C7/22 ,  G11C7/12

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/12 ,  G11C2207/2254

Abstract: A memory device and system supporting command bus training are provided. An operating method of the memory device includes entering into a command bus training mode, receiving a clock signal, a chip selection signal and a first command/address signal, generating an internal clock signal by dividing the clock signal, generating a second command/address signal by latching the first command/address signal at a rising edge or a falling edge of the internal clock signal when a chip selection signal is activated, and outputting the second command/address signal.

公开(公告)号：US20170069364A1

公开(公告)日：2017-03-09

申请号：US15180175

申请日：2016-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun SHIN ,  Tae-Young OH

IPC: G11C8/18 ,  G11C8/10 ,  G11C8/06

CPC classification number: G06F3/06 ,  G06F13/1689 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/22 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

Abstract translation: 存储器系统包括存储器控制器和存储器。 存储器控制器选择性地以第一模式和第二模式操作。 在第一模式中，存储器控制器在多个时钟周期期间连续地发送第一命令。 在第二模式中，存储器控制器将第二命令与第一命令混合并传送第一命令和第二命令的混合。 存储器根据第一或第二模式改变命令锁存时序。