公开(公告)号：US20180083766A1

公开(公告)日：2018-03-22

申请号：US15622689

申请日：2017-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Yoon CHO ,  Joo-Hyun Do ,  Hae-Chul Lee

IPC: H04L7/04 ,  H04J13/00 ,  H04L7/00

CPC classification number: H04L7/042 ,  H04J11/0069 ,  H04J13/0062 ,  H04J2013/0096 ,  H04L7/0087

Abstract: A chip for detecting a synchronization signal generated based on one of a plurality of sequences, which is generated by a sequence generator, the chip including a memory, and a processor connected to the memory may be provided. The processor may be configured to receive the synchronization signal, perform first descrambling the received synchronization signal for a first sequence from among the plurality of sequences by multiplying the received synchronization signal by the first sequence, and perform second descrambling the received synchronization signal for a second sequence, which is a complex conjugate of the first sequence, from among the plurality of sequences of the received synchronization signal by changing a sign of at least one element of a descrambled sequence of the first sequence.