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公开(公告)号：US09197477B2
公开(公告)日：2015-11-24
申请号：US14152297
申请日：2014-01-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Joo-Hyun Do , In-Hyoung Kim
CPC classification number: H04L27/2657 , H04L5/001 , H04L2027/0065
Abstract: A circuit for processing Carrier Aggregation (CA) is provided. The circuit includes a plurality of Component Carrier (CC) processors, each CC processor configured to estimate a frequency offset for a related CC and to compensate the estimated frequency offset, a reference clock generator configured to generate a reference clock using a reference frequency offset as one of frequency offsets output from the plurality of CC processors, a plurality of reception Phase Lock Loop (PLL) units, each reception PLL unit configured to generate a reception carrier frequency for the related CC corresponding to the reference clock, and a plurality of transmission PLL units, each transmission PLL unit configured to generate a transmission carrier frequency for the related CC corresponding to the reference clock.
Abstract translation: 提供了一种用于处理载波聚合（CA）的电路。 所述电路包括多个分量载波（CC）处理器，每个CC处理器被配置为估计相关CC的频率偏移并补偿所估计的频率偏移;参考时钟发生器，被配置为使用参考频率偏移生成参考时钟 从多个CC处理器输出的频率偏移中的一个，多个接收锁相环（PLL）单元，每个接收PLL单元被配置为产生对应于参考时钟的相关CC的接收载波频率，以及多个传输 PLL单元，每个传输PLL单元被配置为针对对应于参考时钟的相关CC产生传输载波频率。
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Patent Agency Ranking
公开(公告)号：USRE48893E1
公开(公告)日：2022-01-11
申请号：US16700389
申请日：2019-12-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Joo-Hyun Do , In-Hyoung Kim
Abstract: A circuit for processing Carrier Aggregation (CA) is provided. The circuit includes a plurality of Component Carrier (CC) processors, each CC processor configured to estimate a frequency offset for a related CC and to compensate the estimated frequency offset, a reference clock generator configured to generate a reference clock using a reference frequency offset as one of frequency offsets output from the plurality of CC processors, a plurality of reception Phase Lock Loop (PLL) units, each reception PLL unit configured to generate a reception carrier frequency for the related CC corresponding to the reference clock, and a plurality of transmission PLL units, each transmission PLL unit configured to generate a transmission carrier frequency for the related CC corresponding to the reference clock.
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公开(公告)号：USRE49805E1
公开(公告)日：2024-01-16
申请号：US17572019
申请日：2022-01-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Joo-Hyun Do , In-Hyoung Kim
CPC classification number: H04L27/2657 , H04L5/001 , H04L2027/0065
Abstract: A circuit for processing Carrier Aggregation (CA) is provided. The circuit includes a plurality of Component Carrier (CC) processors, each CC processor configured to estimate a frequency offset for a related CC and to compensate the estimated frequency offset, a reference clock generator configured to generate a reference clock using a reference frequency offset as one of frequency offsets output from the plurality of CC processors, a plurality of reception Phase Lock Loop (PLL) units, each reception PLL unit configured to generate a reception carrier frequency for the related CC corresponding to the reference clock, and a plurality of transmission PLL units, each transmission PLL unit configured to generate a transmission carrier frequency for the related CC corresponding to the reference clock.
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公开(公告)号：US11190959B2
公开(公告)日：2021-11-30
申请号：US16510190
申请日：2019-07-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hae-Chul Lee , Min-Goo Kim , In-Hyoung Kim , Joo-Hyun Do
IPC: H04W24/08 , H04B17/318 , H04B7/06 , H04L5/00 , H04B17/327
Abstract: Apparatuses, methods, and systems of measuring received power are described, including apparatuses, methods, and systems which can measure received power, even when the subcarrier offset of the measurement bandwidth is different from the subcarrier bandwidth of the cell bandwidth. A method includes receiving, via a transceiver, first channel state information including a first index associated with first subcarrier offset information from a first Base Station (BS); receiving, via the transceiver, a plurality of Resource Blocks (RBs) from a second BS; configuring a second index associated with the plurality of RBs, instead of the first index, when the first index is different from the second index; measuring a received power based on the plurality of RBs from the second BS by using the second index; and identifying the measured received power as a valid received power.
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公开(公告)号：US20180083766A1
公开(公告)日：2018-03-22
申请号：US15622689
申请日：2017-06-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Yoon CHO , Joo-Hyun Do , Hae-Chul Lee
CPC classification number: H04L7/042 , H04J11/0069 , H04J13/0062 , H04J2013/0096 , H04L7/0087
Abstract: A chip for detecting a synchronization signal generated based on one of a plurality of sequences, which is generated by a sequence generator, the chip including a memory, and a processor connected to the memory may be provided. The processor may be configured to receive the synchronization signal, perform first descrambling the received synchronization signal for a first sequence from among the plurality of sequences by multiplying the received synchronization signal by the first sequence, and perform second descrambling the received synchronization signal for a second sequence, which is a complex conjugate of the first sequence, from among the plurality of sequences of the received synchronization signal by changing a sign of at least one element of a descrambled sequence of the first sequence.
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公开(公告)号：US09838237B2
公开(公告)日：2017-12-05
申请号：US14922798
申请日：2015-10-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Joo-Hyun Do , In-Hyoung Kim
CPC classification number: H04L27/2657 , H04L5/001 , H04L2027/0065
Abstract: A circuit for processing Carrier Aggregation (CA) is provided. The circuit includes a plurality of Component Carrier (CC) processors, each CC processor configured to estimate a frequency offset for a related CC and to compensate the estimated frequency offset, a reference clock generator configured to generate a reference clock using a reference frequency offset as one of frequency offsets output from the plurality of CC processors, a plurality of reception Phase Lock Loop (PLL) units, each reception PLL unit configured to generate a reception carrier frequency for the related CC corresponding to the reference clock, and a plurality of transmission PLL units, each transmission PLL unit configured to generate a transmission carrier frequency for the related CC corresponding to the reference clock.
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