公开(公告)号：US20220392781A1

公开(公告)日：2022-12-08

申请号：US17745254

申请日：2022-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Joon KIM ,  Jin Seok LEE ,  Bong Ju LEE ,  Tae Jong YU ,  Tae Sun SHIN ,  Sung Il CHO

IPC: H01L21/67 ,  C23C16/455

Abstract: There is provided a semiconductor device capable of improving the performance and reliability of a device. The semiconductor wafer processing device comprising a chamber, and, a showerhead configured to supply a gas into the chamber, wherein the showerhead includes, a plate, a plurality of first spray hole groups in a first row from a center of the plate, and a second spray hole group in a second row outside the first row, wherein each of the first spray hole groups includes a plurality of first spray holes, and when L is an average value of distances from the center of the plate to each spray hole of each of the first spray hole groups, the number of first spray holes where a distance from the center of the plate is smaller than L is more than the number of first spray holes where the distance from the center of the plate is greater than L.

公开(公告)号：US20180374961A1

公开(公告)日：2018-12-27

申请号：US15849094

申请日：2017-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuk KIM ,  Dae Hyun JANG ,  Seung Pil CHUNG ,  Sung Il CHO

IPC: H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11556 ,  H01L29/10

Abstract: A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.