公开(公告)号：US20190131817A1

公开(公告)日：2019-05-02

申请号：US16170276

申请日：2018-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Soo HA ,  Kun Suk KIM ,  Sung Hoon KIM ,  In Sung HWANG

IPC: H02J7/04

Abstract: An electronic device is provided. The electronic device includes a battery having a rated charging voltage, a rated charging current, and a design capacity, a charging circuit configured to supply power to the battery, and a processor electrically connected to the battery and the charging circuit. The processor is configured to control the charging circuit to charge the battery in different ways based on a plurality of ranges determined based on a full charge capacity (FCC) of the battery, and, when the FCC of the battery is included in a first range from the design capacity to a first capacity lower than the design capacity, control the charging circuit to charge the battery by setting a first voltage lower than the rated charging voltage and setting a first current lower than the rated charging current.

公开(公告)号：US20160276308A1

公开(公告)日：2016-09-22

申请号：US14806604

申请日：2015-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunghwan MIN ,  YoonHa JUNG ,  Jungyong CHOI ,  Sung Hoon KIM

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/367

CPC classification number: H01L23/3128 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3737 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/19107 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor package comprises a bottom package and a top package. The bottom package comprises at least one bottom-package semiconductor device. The top package is on the bottom package and comprises a first side, a second side, a package substrate, a plurality of top-package semiconductor devices, and at least one thermal path. The package substrate is disposed at the first side of the top package. The plurality of top-package semiconductor devices is disposed on the package substrate. The at least one thermal path is disposed between a first top-package semiconductor device and a second top-package semiconductor device, and the thermal path extends from the first side of the top package through the package substrate to the second side of the top package.

Abstract translation: 半导体封装包括底部封装和顶部封装。 底部封装包括至少一个底部封装半导体器件。 顶部封装在底部封装上并且包括第一侧面，第二侧面，封装基板，多个顶部封装半导体器件以及至少一个热路径。 封装衬底设置在顶部封装的第一侧。 多个顶部封装半导体器件设置在封装衬底上。 至少一个热路径设置在第一顶部封装半导体器件和第二顶部封装半导体器件之间，并且热路径从顶部封装的第一侧通过封装衬底延伸到顶部封装的第二侧 。

公开(公告)号：US20130173071A1

公开(公告)日：2013-07-04

申请号：US13733460

申请日：2013-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gye Young LEE ,  Sung Hoon KIM ,  Du San BAEK

IPC: G05B13/02

CPC classification number: G05B13/02 ,  G05B15/02 ,  G05B2219/2642

Abstract: An energy management system and a control method thereof reduces traffic load between the energy management system and display devices by transmitting changes in states of a plurality of home appliances to the display devices in a bundle form, upon occurrence of an event to control an energy level according to variation in electricity price.

Abstract translation: 能量管理系统及其控制方法通过在发生事件以控制能量水平时以多个形式将多个家用电器的状态的变化发送到显示装置来减少能量管理系统和显示装置之间的业务负载 根据电价变动。

公开(公告)号：US20210202456A1

公开(公告)日：2021-07-01

申请号：US17023533

申请日：2020-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Bum KIM ,  Sung Hoon KIM ,  Dae Seok BYEON

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/544 ,  H01L25/00

Abstract: A semiconductor wafer includes unit regions that are repeatedly arranged, and each unit region of the unit regions includes: at least one first chip region; and at least one second chip region spaced apart from the at least one first chip region by a scribe line, wherein a first area size of each of the at least one first chip region is different from a second area size of each of the at least one second chip region from a planar viewpoint.

公开(公告)号：US20230074317A1

公开(公告)日：2023-03-09

申请号：US17696551

申请日：2022-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Won KIM ,  Sung Hoon KIM ,  Ah Reum KIM

IPC: H01L27/11573 ,  H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L27/11529

Abstract: A semiconductor memory device including a memory cell array and a peripheral circuit element configured to control an operation of the memory cell array, and a wiring structure including first and second wiring structures spaced apart from each other on the peripheral circuit element, a first voltage and a second voltage different from the first voltage applied to two opposite ends of the first wiring structure, respectively, and a third voltage different from the first and second voltages applied to the second wiring structure, may be provided. The first wiring structure includes first lines extended in a first direction and spaced apart from each other in a second direction crossing the first direction, the second wiring structure includes second lines extended in the first direction and spaced apart from each other in the second direction, and one of the first lines is between the second lines.