Abstract:
An image sensor is provided and may include a semiconductor substrate having a surface and including trench, the trench extending from the surface into the semiconductor substrate, an insulating pattern provided in the trench and a doped region in the semiconductor substrate and on the insulating patterns. The doped region includes a side portion on a side surface of the insulating pattern, and a bottom portion on a bottom surface of the insulating pattern. A thickness of the side portion of the doped region is from 85% to 115% of a thickness of the bottom portion of the doped region, and a number of dopants per unit area in the side portion of the doped region is from 85% to 115% of a number of dopants per unit area in the bottom portion.
Abstract:
Provided are a semiconductor device having dual transistors, and methods of fabricating a semiconductor device, including sequentially forming an insulating layer and a polysilicon layer on a substrate having a first region and a second region, forming a first mask to cover the polysilicon layer on the second region, injecting at least one n-type impurity into the polysilicon layer on the first region to form an N-region, injecting nitrogen into the N-region, forming a second mask to cover the N-region, and injecting at least one p-type impurity into the polysilicon layer on the second region to form a P-region.
Abstract:
An image sensor includes a substrate including a first surface, a second surface opposite to the first surface, and unit pixels, a deep device isolation portion disposed in the substrate to isolate the unit pixels from each other, and a transfer gate disposed on the first surface and in each of the unit pixels. The deep device isolation portion includes a first conductive pattern extending from the first surface toward the second surface, a first insulating pattern interposed between the first conductive pattern and the substrate, a second conductive pattern extending from the second surface toward the first conductive pattern, and a first fixed charge layer interposed between the second conductive pattern and the substrate.