公开(公告)号：US20230047026A1

公开(公告)日：2023-02-16

申请号：US17867764

申请日：2022-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Soo HA ,  Ju-Youn CHOI ,  In Won O ,  Jun Ho LEE

IPC: H01L23/498 ,  H01L25/16

Abstract: A semiconductor package includes: a first wiring structure including a first wiring layer, and a second wiring layer disposed on the first wiring layer, and connected to a first connecting structure placed disposed on the first wiring layer; a first semiconductor chip disposed on the first wiring structure and connected to the first wiring structure through a first connecting pad disposed on a first side of the first semiconductor chip; a second wiring structure disposed on the first semiconductor chip; and an insulating member disposed between the first and second wiring structures, wherein the first wiring structure further includes a first signal pattern that is electrically connected to the first connecting pad, and the first signal pattern redistributes the first connecting pad to the first connecting structure via the insulating member.

公开(公告)号：US20240234274A1

公开(公告)日：2024-07-11

申请号：US18372257

申请日：2023-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tong Suk KIM ,  Sang Woong LEE ,  Shle-Ge LEE ,  Seung Soo HA ,  Chang Ui HONG

IPC: H01L23/498 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/105 ,  H01L24/16 ,  H01L2224/16225

Abstract: A semiconductor package, including a first structure including a ball array region on a lower surface of the first structure and an external region completely surrounding the ball array region, the ball array region including a passive element region in which solder balls are not disposed and an edge region completely surrounding the passive element region, a first semiconductor chip on an upper surface of the first structure, a passive element in the passive element region on the lower surface of the first structure, the passive element not in the edge region on the lower surface of the first structure, and a first ball array in the edge region on the lower surface of the first structure, the first ball array including two or more first power solder balls supplying power to at least one of the passive element and the first semiconductor chip.