公开(公告)号：US11056193B2

公开(公告)日：2021-07-06

申请号：US16442672

申请日：2019-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Won Yun ,  Jin-Young Kim ,  Il-Han Park ,  Hyun Seo ,  Bong-Soon Lim

IPC: G11C16/16 ,  G11C16/04 ,  H01L27/11582 ,  G11C11/56

Abstract: A memory device includes an array of vertical NAND strings of nonvolatile memory cells, on an underlying substrate. An erase control circuit is provided, which is configured to drive a plurality of bit lines electrically coupled to the array of vertical NAND strings of nonvolatile memory cells with respective erase voltages having unequal magnitudes during an operation to erase the nonvolatile memory cells in the array of vertical NAND strings. This erase control circuit may also be configured to drive a first of the plurality of bit lines with a first erase voltage for a first duration and drive a second of the plurality of bit lines with a second erase voltage for a second duration unequal to the first duration during the operation to erase the nonvolatile memory cells in the array of vertical NAND strings.