公开(公告)号：US20230070191A1

公开(公告)日：2023-03-09

申请号：US17728421

申请日：2022-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Ae KIM ,  Seong Woon KIM ,  Kil Whan LEE ,  Sang Hoon LEE ,  Yong Kwon CHO ,  Sang Hoon HA

IPC: H04N5/235 ,  G06T1/20 ,  G06T1/60 ,  G06T5/00

Abstract: A system on chip and a mobile device are provided. The mobile device comprises a processor configured to receive raw image data, process the raw image data into floating-point format image data, and output the floating-point format image data, a memory configured to store therein the floating-point format image data, and a display processing unit configured to receive the floating-point format image data stored in the memory therefrom, and perform high dynamic range (HDR) processing on the floating-point format image data.

公开(公告)号：US20230169909A1

公开(公告)日：2023-06-01

申请号：US17867033

申请日：2022-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong Woon KIM ,  Kil Whan LEE ,  Sun-Ae KIM ,  Sang Hoon LEE ,  Yong Kwon CHO ,  Sang Hoon HA

IPC: G09G3/20

CPC classification number: G09G3/2096 ,  G09G2360/18 ,  G09G2360/12

Abstract: A display controller includes a resource controller configured to receive layer information about each of a first layer and a second layer that are output at different times through a display panel during a unit frame. The display controller includes a data input direct memory access (DMA) configured to receive first image data corresponding to the first layer and second image data corresponding to the second layer, and a hardware resource configured to receive the first and second image data from the data input DMA, process the received first and second image data according to the layer information, and generate first layer data of the first layer and second layer data of the second layer. The resource controller is configured to control the data input DMA according to the layer information to determine an order in which the first and second image data are provided to the hardware resource.

公开(公告)号：US20180198996A1

公开(公告)日：2018-07-12

申请号：US15913033

申请日：2018-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hoon HA ,  Ji Yong Park ,  Kwang Hyun Lee

IPC: H04N5/357 ,  H04N5/378 ,  H04N5/3745 ,  H04N5/365 ,  H01L27/146 ,  H04N5/363

CPC classification number: H04N5/3575 ,  H01L27/14634 ,  H01L27/14645 ,  H04N5/363 ,  H04N5/3658 ,  H04N5/374 ,  H04N5/37455 ,  H04N5/378

Abstract: A correlated double sampling (CDS) circuit includes a comparator and a first circuit. The comparator including, a first input terminal, a second input terminal, at least one output terminal, and a plurality of first transistors operably coupled between the at least one output terminal and the first and second input terminals. The first circuit includes at least one second transistor, the at least one second transistor operably coupled to the at least one output terminal and one of the first input terminal and the second input terminal, the at least one second transistor having at least one of (i) a different number of layers than the first transistors, and (ii) a different dimension than the first transistors.

公开(公告)号：US20170289475A1

公开(公告)日：2017-10-05

申请号：US15438060

申请日：2017-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hoon HA ,  Ji Yong PARK ,  Kwang Hyun LEE

IPC: H04N5/357 ,  H04N5/378 ,  H04N5/365 ,  H04N5/3745 ,  H01L27/146 ,  H04N5/363

CPC classification number: H04N5/3575 ,  H01L27/14634 ,  H01L27/14645 ,  H04N5/363 ,  H04N5/3658 ,  H04N5/374 ,  H04N5/37455 ,  H04N5/378

Abstract: A correlated double sampling (CDS) circuit includes a comparator and a first circuit. The comparator including, a first input terminal, a second input terminal, at least one output terminal, and a plurality of first transistors operably coupled between the at least one output terminal and the first and second input terminals. The first circuit includes at least one second transistor, the at least one second transistor operably coupled to the at least one output terminal and one of the first input terminal and the second input terminal, the at least one second transistor having at least one of (i) a different number of layers than the first transistors, and (ii) a different dimension than the first transistors.