公开(公告)号：US20240292604A1

公开(公告)日：2024-08-29

申请号：US18386654

申请日：2023-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiseong KIM ,  JUNSOO KIM ,  DAEHYUN MOON ,  SUNGHO JANG

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor device includes a substrate including cell regions, active patterns adjacent to each other in first and second directions that are parallel to a lower surface of the substrate and intersect each other on the cell regions, a shield pattern surrounding side surfaces of the active patterns, a first isolation pattern surrounding the active patterns between the active patterns and the shield pattern, second isolation patterns between adjacent active patterns in the first direction, and word lines crossing the active patterns and the shield pattern in the second direction.

公开(公告)号：US20220070992A1

公开(公告)日：2022-03-03

申请号：US17242022

申请日：2021-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGHO JANG ,  YOONJAE KIM ,  HYUCK SHIN ,  DONGHYUB LEE ,  KUL INN

IPC: H05G2/00 ,  H01S3/223 ,  G03F7/20

Abstract: A method of manufacturing a semiconductor includes generating plasma in an amplifying tube using gas as a gain medium; detecting a state of the plasma generated in the amplifying tube; determining a virtual laser gain based on the detected state of the plasma; controlling the state of the plasma such that the virtual laser gain is within a target range; and manufacturing the semiconductor device including performing an exposure process on a substrate using a laser beam output from the amplifying tube adjusted to have the virtual laser gain within the target range.

公开(公告)号：US20240306371A1

公开(公告)日：2024-09-12

申请号：US18462553

申请日：2023-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAEIN JUNG ,  SUNGHO JANG ,  JISEOK KWON ,  SEUNG HWAN KIM ,  SEUNGHO HONG

IPC: H10B12/00

CPC classification number: H10B12/36 ,  H10B12/315 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488

Abstract: A semiconductor device includes a semiconductor substrate including a first semiconductor material, a gate structure on the semiconductor substrate, and a semiconductor pattern including a second semiconductor material, between the semiconductor substrate and the gate structure. The semiconductor pattern is in contact with the semiconductor substrate, the gate structure passes through a portion of the semiconductor pattern, and is spaced apart from the semiconductor substrate, and the first semiconductor material is different from the second semiconductor material.

公开(公告)号：US20240251549A1

公开(公告)日：2024-07-25

申请号：US18456655

申请日：2023-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGGYU KO ,  HYUCKCHAI JUNG ,  SANG-IL HAN ,  JUNGJIN PARK ,  SUHYUN KIM ,  CHUL LEE ,  SUNGHO JANG ,  HYEONGWON JANG

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/315 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488

Abstract: A semiconductor device includes a substrate including a peripheral active pattern defined by a device isolation layer, a gate structure on the peripheral active pattern, and a gate spacer covering at least a portion of a side surface of the gate structure. The gate structure includes an insulating pattern structure and a metal pattern structure on the insulating pattern structure. The insulating pattern structure includes a recess having a maximum depth in a first direction parallel to a top surface of the substrate at a first height. The insulating pattern structure includes a first gate insulating pattern and a high-k dielectric layer, which are sequentially stacked on the top surface of the substrate. The gate spacer includes a protrusion inserted in the recess.

公开(公告)号：US20240243059A1

公开(公告)日：2024-07-18

申请号：US18372881

申请日：2023-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGHO JANG ,  JUNSOO KIM ,  ILGWEON KIM ,  DONGSOO WOO ,  MOONYOUNG JEONG ,  JOON HAN

IPC: H01L23/528

CPC classification number: H01L23/528 ,  H10B12/482

Abstract: A semiconductor device may include a substrate including an insulating substrate. A semiconductor layer is on the substrate. An active pattern is on the semiconductor layer. A bit line is disposed in the insulating substrate. The bit line extends along a first direction parallel to a bottom surface of the substrate. A buried node contact penetrates the semiconductor layer in a direction perpendicular to the bottom surface of the substrate. A word line penetrates the active pattern in a second direction that is parallel to the bottom surface of the substrate and crosses the first direction. The active pattern may be connected to the bit line through the buried node contact. A top surface of the buried node contact may be higher than a bottom surface of the active pattern.

公开(公告)号：US20240128102A1

公开(公告)日：2024-04-18

申请号：US18125853

申请日：2023-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGHO JANG ,  HYUNGJIN KIM ,  MINHWAN SEO ,  AKINORI OKUBO ,  SANGMIN LEE ,  SINYONG LEE ,  WONDON JOO ,  SANGJOON HONG

IPC: H01L21/67 ,  G01B11/06

CPC classification number: H01L21/67259 ,  G01B11/0608

Abstract: An apparatus monitoring semiconductor manufacturing equipment includes; an optical detector, a light generator generating light along a first optical path towards a semiconductor substrate, wherein upon irradiating the semiconductor substrate, the light becomes reflected light along a second optical path away from the semiconductor substrate and towards the optical detector, a first grating reticle between the light generator and the semiconductor substrate and including first slits having a first pitch and second slits having a second pitch different from the first pitch, a second grating reticle between the semiconductor substrate and the optical detector and including third slits having a third pitch different from the first pitch and the second pitch, wherein the optical detector determines a positional attribute of the semiconductor substrate in relation to a first pattern and a second pattern, the first pattern corresponds to a first portion of light/reflected light sequentially passing through the first slits and the third slits, and the second pattern corresponds to a second portion of light/reflected light sequentially passing through the second slits and the third slits.