公开(公告)号：US20240315008A1

公开(公告)日：2024-09-19

申请号：US18383201

申请日：2023-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUN-BUM LEE ,  JUNSOO KIM ,  JAE HYUN CHOI ,  DONGSIK KONG ,  JIHYE KWON ,  TAEYOON AN ,  Hyun Seung CHOI

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315

Abstract: A semiconductor memory device is provided. The semiconductor device may include a semiconductor substrate having a device isolation trench defining active regions, a device isolation layer disposed in the device isolation trench, gate trenches extending in a first direction and crossing the active regions of the semiconductor substrate and the device isolation layer, word lines disposed in the gate trenches, respectively, each of the gate trenches may include first trench sections in the active regions and second trench sections in the device isolation layer, the first trench sections may have a first depth, and the second trench section may have a second depth greater than the first depth, the device isolation layer may include a lower portion positioned at a level lower than bottom surfaces of the first trench sections and an upper portion on the lower portion, and the lower portion may be formed of a dielectric material having a lower dielectric constant than that of the upper portion.

公开(公告)号：US20240243059A1

公开(公告)日：2024-07-18

申请号：US18372881

申请日：2023-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGHO JANG ,  JUNSOO KIM ,  ILGWEON KIM ,  DONGSOO WOO ,  MOONYOUNG JEONG ,  JOON HAN

IPC: H01L23/528

CPC classification number: H01L23/528 ,  H10B12/482

Abstract: A semiconductor device may include a substrate including an insulating substrate. A semiconductor layer is on the substrate. An active pattern is on the semiconductor layer. A bit line is disposed in the insulating substrate. The bit line extends along a first direction parallel to a bottom surface of the substrate. A buried node contact penetrates the semiconductor layer in a direction perpendicular to the bottom surface of the substrate. A word line penetrates the active pattern in a second direction that is parallel to the bottom surface of the substrate and crosses the first direction. The active pattern may be connected to the bit line through the buried node contact. A top surface of the buried node contact may be higher than a bottom surface of the active pattern.

公开(公告)号：US20220139443A1

公开(公告)日：2022-05-05

申请号：US17470641

申请日：2021-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNSOO KIM ,  MINWOO KWON

IPC: G11C11/408 ,  H01L27/108

Abstract: An integrated circuit device includes a plurality of memory cells each including a channel region, a first sub-word line, a second sub-word line, and a storage element. A word line driving circuit is configured to drive the first and sub-word lines. The word line driving circuit includes a PMOS transistor, an NMOS transistor, a keeping NMOS transistor, and a first keeping PMOS transistor. A negative voltage is applied to a source of the NMOS transistor, the negative voltage is applied to a source of the keeping NMOS transistor, the first sub-word line is connected to a source of the first keeping PMOS transistor, the second sub-word line is connected to a drain of the first keeping PMOS transistor, and a negative voltage is applied to a gate of the first keeping PMOS transistor.

公开(公告)号：US20240292604A1

公开(公告)日：2024-08-29

申请号：US18386654

申请日：2023-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiseong KIM ,  JUNSOO KIM ,  DAEHYUN MOON ,  SUNGHO JANG

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor device includes a substrate including cell regions, active patterns adjacent to each other in first and second directions that are parallel to a lower surface of the substrate and intersect each other on the cell regions, a shield pattern surrounding side surfaces of the active patterns, a first isolation pattern surrounding the active patterns between the active patterns and the shield pattern, second isolation patterns between adjacent active patterns in the first direction, and word lines crossing the active patterns and the shield pattern in the second direction.

公开(公告)号：US20230014583A1

公开(公告)日：2023-01-19

申请号：US17935121

申请日：2022-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNSOO KIM ,  Minwoo Kwon

IPC: G11C11/408 ,  H01L27/108

Abstract: An integrated circuit device includes a plurality of memory cells each including a channel region, a first sub-word line, a second sub-word line, and a storage element. A word line driving circuit is configured to drive the first and sub-word lines. The word line driving circuit includes a PMOS transistor, an NMOS transistor, a keeping NMOS transistor, and a first keeping PMOS transistor. A negative voltage is applied to a source of the NMOS transistor, the negative voltage is applied to a source of the keeping NMOS transistor, the first sub-word line is connected to a source of the first keeping PMOS transistor, the second sub-word line is connected to a drain of the first keeping PMOS transistor, and a negative voltage is applied to a gate of the first keeping PMOS transistor.