公开(公告)号：US20240341083A1

公开(公告)日：2024-10-10

申请号：US18493196

申请日：2023-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Bum LEE ,  Dongsik KONG ,  Jihye KWON ,  Junsoo KIM ,  Jae Hyun CHOI ,  Hyun Seung CHOI

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315 ,  H10B12/482

Abstract: Active regions defined by device isolation layer are provided on a substrate. A word line crossing the active regions and a gate dielectric layer between the word line and the active regions are provided. A capping insulating pattern covering an upper surface of the word line and a bit line on the word line are provided. The word line may include a first conductive pattern and a second conductive pattern on the first conductive pattern. The first conductive pattern may include a first metal element. The second conductive pattern may include the first metal element, a work function adjustment element, and a diffusion barrier element. An atomic radius of the diffusion barrier element may be smaller than an atomic radius of the first metal element.

公开(公告)号：US20240315008A1

公开(公告)日：2024-09-19

申请号：US18383201

申请日：2023-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUN-BUM LEE ,  JUNSOO KIM ,  JAE HYUN CHOI ,  DONGSIK KONG ,  JIHYE KWON ,  TAEYOON AN ,  Hyun Seung CHOI

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315

Abstract: A semiconductor memory device is provided. The semiconductor device may include a semiconductor substrate having a device isolation trench defining active regions, a device isolation layer disposed in the device isolation trench, gate trenches extending in a first direction and crossing the active regions of the semiconductor substrate and the device isolation layer, word lines disposed in the gate trenches, respectively, each of the gate trenches may include first trench sections in the active regions and second trench sections in the device isolation layer, the first trench sections may have a first depth, and the second trench section may have a second depth greater than the first depth, the device isolation layer may include a lower portion positioned at a level lower than bottom surfaces of the first trench sections and an upper portion on the lower portion, and the lower portion may be formed of a dielectric material having a lower dielectric constant than that of the upper portion.