公开(公告)号：US20240341083A1

公开(公告)日：2024-10-10

申请号：US18493196

申请日：2023-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Bum LEE ,  Dongsik KONG ,  Jihye KWON ,  Junsoo KIM ,  Jae Hyun CHOI ,  Hyun Seung CHOI

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315 ,  H10B12/482

Abstract: Active regions defined by device isolation layer are provided on a substrate. A word line crossing the active regions and a gate dielectric layer between the word line and the active regions are provided. A capping insulating pattern covering an upper surface of the word line and a bit line on the word line are provided. The word line may include a first conductive pattern and a second conductive pattern on the first conductive pattern. The first conductive pattern may include a first metal element. The second conductive pattern may include the first metal element, a work function adjustment element, and a diffusion barrier element. An atomic radius of the diffusion barrier element may be smaller than an atomic radius of the first metal element.

公开(公告)号：US20160308000A1

公开(公告)日：2016-10-20

申请号：US15194066

申请日：2016-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junsoo KIM ,  Dongjin LEE ,  Dongsoo WOO ,  Jun-Bum LEE ,  SANG-IL HAN

IPC: H01L29/06 ,  H01L27/24 ,  H01L27/108 ,  H01L27/22 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/0653 ,  H01L27/088 ,  H01L27/10805 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/228 ,  H01L27/2436 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device may include a semiconductor substrate including an active region defined by a trench, a device isolation layer provided in the trench to surround the active region, a gate electrode extending in a direction crossing the active region, and formed on the active region and the device isolation layer, and a gate insulating layer between the active region and the gate electrode. The active region may have a first conductivity type, and the device isolation layer may include a first silicon oxide layer on an inner surface of the first trench and a different layer, selected from one of first metal oxide layer and a negatively-charged layer, on the first silicon oxide layer.