公开(公告)号：US20240165769A1

公开(公告)日：2024-05-23

申请号：US18196178

申请日：2023-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MYUNGJAE JANG ,  DONGHOON KWON ,  JONGHYUK PARK

IPC: B24B57/02 ,  B24B37/04

CPC classification number: B24B57/02 ,  B24B37/04

Abstract: A substrate polishing apparatus includes; a platen including an upper surface configured to perform a polishing process on a semiconductor substrate, a slurry supply configured to supply slurry to the upper surface of the platen, wherein the slurry includes aqueous solution and abrasive particles, a collection pipe disposed under the platen and configured to guide the slurry, wherein the collection pipe includes a vertical guide pipe and a lateral guide pipe, a collection device disposed on an outer surface of the collection pipe, wherein the collection device includes an alternating arrangement of magnetic separators configured to separate the abrasive particles from the slurry using an electromagnetic force and sonicators configured to decompose the abrasive particles, and a collection tank connected to the collection pipe and configured to store the abrasive particles separated from the slurry by the collection device.

公开(公告)号：US20240332059A1

公开(公告)日：2024-10-03

申请号：US18390026

申请日：2023-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngin KIM ,  BYOUNGHO KWON ,  Yeil KIM ,  JONGHYUK PARK ,  JIN-WOO BAE ,  KYOUNGJOON SONG ,  MYUNGJAE JANG ,  Byungsoo JOO

IPC: H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L21/768

CPC classification number: H01L21/762 ,  H01L21/30625 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76831 ,  H01L21/76832

Abstract: A method of fabricating a semiconductor device includes forming, in a semiconductor substrate, a device isolation trench defining active regions, forming a first liner dielectric layer covering a top surface of the semiconductor substrate and an inner wall of the device isolation trench, forming a second liner dielectric layer covering the first liner dielectric layer, forming a buried dielectric layer filling the device isolation trench, performing a polishing process on the second liner dielectric layer and the buried dielectric layer to form a device isolation structure, forming a mask pattern running across the active regions, and partially patterning the active regions and the device isolation structure to form gate trenches. After the polishing process, the first liner dielectric layer, the second liner dielectric layer, and the buried dielectric layer have their top surfaces formed by the polishing process coplanar with each other.