公开(公告)号：US20240213160A1

公开(公告)日：2024-06-27

申请号：US18535143

申请日：2023-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungpil PARK ,  Doohwan PARK ,  Sanghyun LEE ,  Hyeonmin JEON

IPC: H01L23/532 ,  H01L23/522

CPC classification number: H01L23/5329 ,  H01L23/5226 ,  H01L23/49816

Abstract: A semiconductor device includes a first wiring level layer including a lower wiring layer, a second wiring level layer on the first wiring level layer and including an upper wiring layer, a via level layer positioned between the first wiring level layer and the second wiring level layer and including a via connecting the lower wiring layer to the upper wiring layer, and a reinforcing insulating layer positioned between the lower wiring layer and the upper wiring layer in the via level layer.

公开(公告)号：US20220068810A1

公开(公告)日：2022-03-03

申请号：US17221191

申请日：2021-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghun LIM ,  Wookyung YOU ,  Kyoungwoo LEE ,  Juyoung JUNG ,  Il Sup KIM ,  Chin KIM ,  Kyoungpil PARK ,  Jinhyung PARK

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/06

Abstract: A semiconductor device including a transistor on a substrate; an interlayer insulating layer on the transistor; a first metal-containing layer on the interlayer insulating layer; and a second metal-containing layer on the first metal-containing layer, wherein the second metal-containing layer includes a resistor, the resistor includes a first insulating layer on the first metal-containing layer; a resistor metal layer on the first insulating layer; and a second insulating layer on the resistor metal layer, and the resistor metal layer includes a recessed side surface.