公开(公告)号：US09147461B1

公开(公告)日：2015-09-29

申请号：US14185264

申请日：2014-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Youn Youn ,  So-Young Kim ,  Kwang-Sook Noh ,  Sang-Jae Rhee ,  Hyun-Chul Yoon ,  Yoon-Jae Lee ,  Jung-Bae Lee ,  Joo-Sun Choi

IPC: G11C11/40 ,  G11C11/406 ,  G11C8/18 ,  G06F11/10 ,  G11C11/22

CPC classification number: G11C11/40626 ,  G06F11/106 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C11/22 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409

Abstract: A semiconductor memory device includes a memory cell array and a refresh control circuit. The refresh circuit is configured to: perform a second burst refresh operation on the memory cell rows after the memory cell rows exit from a self refresh operation, and not perform the second burst refresh operation on the memory cell rows after the memory cell rows exit from a self refresh operation. Whether the refresh control circuit performs or does not perform the second burst refresh operation is based on a comparison between an entering time for the self refresh operation of the memory cell rows and a reference time.

Abstract translation: 半导体存储器件包括存储单元阵列和刷新控制电路。 刷新电路被配置为：在存储单元行从自刷新操作退出之后对存储单元行执行第二突发刷新操作，并且在存储单元行从退出之后不对存储单元行执行第二次突发刷新操作 自刷新操作。 刷新控制电路执行还是不执行第二脉冲串刷新操作是基于存储单元行的自刷新操作的输入时间与参考时间之间的比较。