公开(公告)号：US20240234500A9

公开(公告)日：2024-07-11

申请号：US18141990

申请日：2023-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiho Yoo ,  Kihyung Ko ,  Junsoo Kim ,  Hyunsup Kim ,  Jihoon Cha

IPC: H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775

Abstract: A semiconductor device may include an active pattern on a substrate; an isolation pattern on the substrate, the isolation pattern covering opposite sidewalls of the active pattern; a liner on the isolation pattern, a liner including a material different from the isolation pattern; a gate structure contacting an upper surface of the active pattern and an upper surface of the liner; and a plurality of channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the plurality of channels extending through the gate structure.

公开(公告)号：US20240136396A1

公开(公告)日：2024-04-25

申请号：US18141990

申请日：2023-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiho Yoo ,  Kihyung Ko ,  Junsoo Kim ,  Hyunsup Kim ,  Jihoon Cha

IPC: H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775

Abstract: A semiconductor device may include an active pattern on a substrate; an isolation pattern on the substrate, the isolation pattern covering opposite sidewalls of the active pattern; a liner on the isolation pattern, a liner including a material different from the isolation pattern; a gate structure contacting an upper surface of the active pattern and an upper surface of the liner; and a plurality of channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the plurality of channels extending through the gate structure.

公开(公告)号：US20240421207A1

公开(公告)日：2024-12-19

申请号：US18670738

申请日：2024-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiho Yoo ,  Kihyung Ko ,  Jihoon Cha

IPC: H01L29/423 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a substrate insulating layer having a lower insulating pattern protruding from an upper surface of the substrate insulating layer and extending in a first direction; a semiconductor pattern extending on the lower insulating pattern of the substrate insulating layer in the first direction; a plurality of channel layers stacked on the semiconductor pattern and spaced apart from each other in a direction perpendicular to the upper surface of the substrate insulating layer; a gate structure intersecting the semiconductor pattern, extending in a second direction crossing the first direction, and surrounding the plurality of channel layers; first and second source/drain regions disposed on the semiconductor pattern on both sides of the gate structure; and an intermediate insulating pattern disposed between the lower insulating pattern and the semiconductor pattern and having a thickness equal to or less than a distance between the plurality of channel layers.