公开(公告)号：US10896967B2

公开(公告)日：2021-01-19

申请号：US16404996

申请日：2019-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-sic Yoon ,  Dong-oh Kim ,  Je-min Park ,  Ki-seok Lee

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/51

Abstract: An integrated circuit device includes a gate stack structure on a base layer, the gate stack structure having a gate insulating layer with a first dielectric layer on the base layer and having first relative permittivity, and a gate structure on the gate insulating layer, and a gate spacer structure on opposite side walls of the gate stack structure and on the base layer, the gate spacer structure including a buried dielectric layer buried in a recess hole of the gate insulating layer at a lower portion of the gate spacer structure on the base layer, and the buried dielectric layer including a same material as the first dielectric layer.

公开(公告)号：US20190097007A1

公开(公告)日：2019-03-28

申请号：US15914611

申请日：2018-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-hyeok AHN ,  Eun-jung Kim ,  Hui-jung Kim ,  Ki-seok Lee ,  Bong-soo Kim ,  Myeong-dong Lee ,  Sung-hee Han ,  Yoo-sang Hwang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L21/762 ,  H01L21/74

Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.

公开(公告)号：US10784266B2

公开(公告)日：2020-09-22

申请号：US16181510

申请日：2018-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-oh Kim ,  Ki-seok Lee ,  Chan-sic Yoon ,  Je-min Park ,  Woo-song Ahn

IPC: H01L27/108 ,  H01L23/538 ,  H01L29/49 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L29/66

Abstract: An integrated circuit device includes: a substrate having a cell array area, which includes a first active region, and a peripheral circuit area, which includes a second active region; a direct contact connected to the first active region in the cell array area; a bit line structure connected to the direct contact in the cell array area; and a peripheral circuit gate structure on the second active region in the peripheral circuit area, wherein the peripheral circuit gate structure includes two doped semiconductor layers each being doped with a charge carrier impurity having different doping concentrations from each other.

公开(公告)号：US20190189617A1

公开(公告)日：2019-06-20

申请号：US16014118

申请日：2018-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-jung KIM ,  Sung-hee Han ,  Ki-seok Lee ,  Bong-soo Kim ,  Yoo-sang Hwang

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10817 ,  H01L27/10852 ,  H01L28/91

Abstract: An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.

公开(公告)号：US11152369B2

公开(公告)日：2021-10-19

申请号：US16851957

申请日：2020-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Sung-hee Han ,  Ki-seok Lee ,  Bong-Soo Kim ,  Yoo-sang Hwang

IPC: H01L27/108 ,  H01L49/02

Abstract: An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.

公开(公告)号：US10541302B2

公开(公告)日：2020-01-21

申请号：US15881863

申请日：2018-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-sic Yoon ,  Ho-in Lee ,  Ki-seok Lee ,  Je-min Park

IPC: H01L21/762 ,  H01L29/06 ,  H01L27/108 ,  G11C11/408

Abstract: An integrated circuit device includes a substrate having a first region and a second region separated from each other along a direction parallel to an upper surface of the substrate. An interface device isolation layer fills an interface trench in an interface region between the first region and the second region and defines a portion of a first active area positioned in the first region and a portion of a second active area positioned in the second region. An insulation pattern extends from the first region to an upper portion of the interface device isolation layer. The insulation pattern covers the first active area and at least a portion of the interface device isolation layer. The insulation pattern defines an undercut area on an upper surface of the interface device isolation layer. A buried pattern substantially fills the undercut region.

公开(公告)号：US10128252B2

公开(公告)日：2018-11-13

申请号：US15646540

申请日：2017-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-seok Lee ,  Dae-ik Kim ,  Yoo-sang Hwang ,  Bong-soo Kim ,  Je-min Park

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/167 ,  H01L29/36 ,  G11C11/4091 ,  G11C11/408 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including a cell active region and a peripheral active region, a direct contact arranged on a cell insulating pattern formed on the substrate and connected to the cell active region, a bit line structure including a thin conductive pattern, contacting a top surface of the direct contact and extending in one direction, and a peripheral gate structure in the peripheral active region. The peripheral gate structure include a stacked structure of a peripheral gate insulating pattern and a peripheral gate conductive pattern, the thin conductive pattern includes a first material and the peripheral gate conductive pattern include the first material, and a level of an upper surface of the thin conductive pattern is lower than a level of an upper surface of the peripheral gate conductive pattern.

公开(公告)号：US20190355728A1

公开(公告)日：2019-11-21

申请号：US16181510

申请日：2018-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-oh Kim ,  Ki-seok Lee ,  Chan-sic Yoon ,  Je-min Park ,  Woo-song Ahn

IPC: H01L27/108 ,  H01L23/538 ,  H01L29/49

Abstract: An integrated circuit device includes: a substrate having a cell array area, which includes a first active region, and a peripheral circuit area, which includes a second active region; a direct contact connected to the first active region in the cell array area; a bit line structure connected to the direct contact in the cell array area; and a peripheral circuit gate structure on the second active region in the peripheral circuit area, wherein the peripheral circuit gate structure includes two doped semiconductor layers each being doped with a charge carrier impurity having different doping concentrations from each other.

公开(公告)号：US20180350905A1

公开(公告)日：2018-12-06

申请号：US15881863

申请日：2018-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-sic Yoon ,  Ho-in Lee ,  Ki-seok Lee ,  Je-min Park

IPC: H01L29/06 ,  H01L27/108 ,  H01L21/762

CPC classification number: H01L29/0649 ,  G11C11/4085 ,  H01L21/76232 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897

Abstract: An integrated circuit device includes a substrate having a first region and a second region separated from each other along a direction parallel to an upper surface of the substrate. An interface device isolation layer fills an interface trench in an interface region between the first region and the second region and defines a portion of a first active area positioned in the first region and a portion of a second active area positioned in the second region. An insulation pattern extends from the first region to an upper portion of the interface device isolation layer. The insulation pattern covers the first active area and at least a portion of the interface device isolation layer. The insulation pattern defines an undercut area on an upper surface of the interface device isolation layer. A buried pattern substantially fills the undercut region.

公开(公告)号：US20180175143A1

公开(公告)日：2018-06-21

申请号：US15833031

申请日：2017-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-sic YOON ,  Ki-seok Lee ,  Ki-wook Jung ,  Dong-oh Kim ,  Ho-in Lee ,  Je-min Park ,  Seok-han Park ,  Augustin Hong ,  Ju-yeon Jang ,  Hyeon-ok Jung ,  Yu-jin Seo

IPC: H01L29/06 ,  H01L27/092 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/0206 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/4236

Abstract: A semiconductor device including a substrate with a first trench, a first insulation liner on inner flanks of the first trench, and a second insulation liner on inner flanks of a first sub trench, the first insulation trench defined by the first insulation liner in the first trench, a top level of the second insulation liner that adjoins the inner flanks of the first sub trench in a direction perpendicular to a top surface of the substrate being different from the top surface of the substrate outside the first trench, may be provided.