公开(公告)号：US20180175045A1

公开(公告)日：2018-06-21

申请号：US15646540

申请日：2017-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-seok LEE ,  Dae-ik Kim ,  Yoo-sang Hwang ,  Bong-soo Kim ,  Je-min Park

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/167 ,  H01L29/36 ,  G11C11/4091 ,  G11C11/408

CPC classification number: H01L27/10897 ,  G11C11/4085 ,  G11C11/4091 ,  H01L23/528 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894 ,  H01L29/167 ,  H01L29/36 ,  H01L29/42376

Abstract: A semiconductor device includes a substrate including a cell active region and a peripheral active region, a direct contact arranged on a cell insulating pattern formed on the substrate and connected to the cell active region, a bit line structure including a thin conductive pattern, contacting a top surface of the direct contact and extending in one direction, and a peripheral gate structure in the peripheral active region. The peripheral gate structure include a stacked structure of a peripheral gate insulating pattern and a peripheral gate conductive pattern, the thin conductive pattern includes a first material and the peripheral gate conductive pattern include the first material, and a level of an upper surface of the thin conductive pattern is lower than a level of an upper surface of the peripheral gate conductive pattern.

公开(公告)号：US20200243532A1

公开(公告)日：2020-07-30

申请号：US16851957

申请日：2020-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung KIM ,  Sung-hee HAN ,  Ki-seok LEE ,  Bong-Soo KIM ,  Yoo-sang HWANG

IPC: H01L27/108 ,  H01L49/02

Abstract: An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.

公开(公告)号：US20200091305A1

公开(公告)日：2020-03-19

申请号：US16404996

申请日：2019-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-sic YOON ,  Dong-oh KIM ,  Je-min PARK ,  Ki-seok LEE

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66

Abstract: An integrated circuit device includes a gate stack structure on a base layer, the gate stack structure having a gate insulating layer with a first dielectric layer on the base layer and having first relative permittivity, and a gate structure on the gate insulating layer, and a gate spacer structure on opposite side walls of the gate stack structure and on the base layer, the gate spacer structure including a buried dielectric layer buried in a recess hole of the gate insulating layer at a lower portion of the gate spacer structure on the base layer, and the buried dielectric layer including a same material as the first dielectric layer.

公开(公告)号：US20180350818A1

公开(公告)日：2018-12-06

申请号：US15884504

申请日：2018-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-sic YOON ,  Ki-seok LEE ,  Jung-hyun KIM ,  Je-min PARK

IPC: H01L27/108

CPC classification number: H01L27/10888 ,  H01L21/02697 ,  H01L21/768 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897

Abstract: A semiconductor device includes first wiring line patterns on a support layer, second wiring line patterns on the first wiring line patterns, and a multiple insulation pattern. The first wiring line patterns extend in a first direction and are spaced apart from each other in a second direction. The support layer includes first contact hole patterns between the first wiring line patterns that are spaced apart from each other in the first and second directions. The second wiring line patterns extend in the second direction perpendicular and are spaced apart from each other in the first direction. The multiple insulation pattern is on an upper surface of the support layer where the first contact hole patterns are not formed, arranged in a third direction perpendicular to the first direction and the second direction, and between the first wiring line patterns and the second wiring line patterns.